JP2000020305A5 - - Google Patents

Download PDF

Info

Publication number
JP2000020305A5
JP2000020305A5 JP1999144417A JP14441799A JP2000020305A5 JP 2000020305 A5 JP2000020305 A5 JP 2000020305A5 JP 1999144417 A JP1999144417 A JP 1999144417A JP 14441799 A JP14441799 A JP 14441799A JP 2000020305 A5 JP2000020305 A5 JP 2000020305A5
Authority
JP
Japan
Prior art keywords
configurable
control signal
input
data
data path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999144417A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000020305A (ja
Filing date
Publication date
Priority claimed from US09/086,741 external-priority patent/US6138229A/en
Application filed filed Critical
Publication of JP2000020305A publication Critical patent/JP2000020305A/ja
Publication of JP2000020305A5 publication Critical patent/JP2000020305A5/ja
Pending legal-status Critical Current

Links

JP11144417A 1998-05-29 1999-05-25 カスタマイズ可能な命令セット・プロセッサの方法およびア―キテクチャ Pending JP2000020305A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US086741 1998-05-29
US09/086,741 US6138229A (en) 1998-05-29 1998-05-29 Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units

Publications (2)

Publication Number Publication Date
JP2000020305A JP2000020305A (ja) 2000-01-21
JP2000020305A5 true JP2000020305A5 (enExample) 2006-07-06

Family

ID=22200594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11144417A Pending JP2000020305A (ja) 1998-05-29 1999-05-25 カスタマイズ可能な命令セット・プロセッサの方法およびア―キテクチャ

Country Status (2)

Country Link
US (1) US6138229A (enExample)
JP (1) JP2000020305A (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6279045B1 (en) * 1997-12-29 2001-08-21 Kawasaki Steel Corporation Multimedia interface having a multimedia processor and a field programmable gate array
US6477683B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US7620832B2 (en) * 2000-09-20 2009-11-17 Mips Technologies, Inc. Method and apparatus for masking a microprocessor execution signature
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
US7162621B2 (en) * 2001-02-21 2007-01-09 Mips Technologies, Inc. Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
US7711763B2 (en) 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
US7237097B2 (en) 2001-02-21 2007-06-26 Mips Technologies, Inc. Partial bitwise permutations
US7181484B2 (en) * 2001-02-21 2007-02-20 Mips Technologies, Inc. Extended-precision accumulation of multiplier output
US7599981B2 (en) * 2001-02-21 2009-10-06 Mips Technologies, Inc. Binary polynomial multiplier
US7318145B1 (en) 2001-06-01 2008-01-08 Mips Technologies, Inc. Random slip generator
JP2003015897A (ja) * 2001-06-29 2003-01-17 Yamaha Corp 制御装置、メディア記録装置、制御方法、制御プログラム、およびメモリ書換えプログラム
US7043495B1 (en) * 2001-07-27 2006-05-09 Cypress Semiconductor Corp. Techniques for JEDEC file information integrity and preservation of device programming specifications
GB2382175A (en) * 2001-11-20 2003-05-21 Hewlett Packard Co Reconfigurable processor
JP2003316838A (ja) * 2002-04-19 2003-11-07 Nec Electronics Corp システムｌｓｉの設計方法及びこれを記憶した記録媒体
EP1408405A1 (en) * 2002-10-11 2004-04-14 STMicroelectronics S.r.l. "A reconfigurable control structure for CPUs and method of operating same"
US20040139297A1 (en) * 2003-01-10 2004-07-15 Huppenthal Jon M. System and method for scalable interconnection of adaptive processor nodes for clustered computer systems
US20060265571A1 (en) * 2003-03-05 2006-11-23 Thomas Bosch Processor with different types of control units for jointly used resources
WO2004092913A2 (en) * 2003-04-14 2004-10-28 Arc International Digital processor apparatus with code compression and method
US20050228966A1 (en) * 2004-03-16 2005-10-13 Kabushiki Kaisha Toshiba Processor system and data processing method
US9860055B2 (en) * 2006-03-22 2018-01-02 Synopsys, Inc. Flexible architecture for processing of large numbers and method therefor
WO2008013968A2 (en) * 2006-07-28 2008-01-31 Vast Systems Technology Corporation Virtual processor generation model for co-simulation
US7529909B2 (en) * 2006-12-28 2009-05-05 Microsoft Corporation Security verified reconfiguration of execution datapath in extensible microcomputer
WO2008091575A2 (en) 2007-01-22 2008-07-31 Vast Systems Technology Corporation Method and system for modeling a bus for a system design incorporating one or more programmable processors
JP2011028543A (ja) * 2009-07-27 2011-02-10 Renesas Electronics Corp 情報処理システム及びその情報処理方法
US9851969B2 (en) 2010-06-24 2017-12-26 International Business Machines Corporation Function virtualization facility for function query of a processor
US10521231B2 (en) 2010-06-24 2019-12-31 International Business Machines Corporation Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor
US20120226890A1 (en) * 2011-02-24 2012-09-06 The University Of Tokyo Accelerator and data processing method
FR3012235B1 (fr) * 2013-10-17 2017-06-16 St Microelectronics Sa Procede de securisation d'un jeu d'instructions executables et/ou d'un schema d'adressage d'un systeme informatique et systeme correspondant
US11061853B2 (en) 2015-12-08 2021-07-13 Via Alliance Semiconductor Co., Ltd. Processor with memory controller including dynamically programmable functional unit
US10642617B2 (en) 2015-12-08 2020-05-05 Via Alliance Semiconductor Co., Ltd. Processor with an expandable instruction set architecture for dynamically configuring execution resources
US10268586B2 (en) 2015-12-08 2019-04-23 Via Alliance Semiconductor Co., Ltd. Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests
US10255462B2 (en) 2016-06-17 2019-04-09 Arm Limited Apparatus and method for obfuscating power consumption of a processor
US10942742B1 (en) * 2018-12-11 2021-03-09 Amazon Technologies, Inc. Hardware engine with configurable instructions
US11651111B2 (en) 2020-09-25 2023-05-16 Intel Corporation Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476626A (ja) * 1990-07-13 1992-03-11 Toshiba Corp マイクロコンピュータ
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5426378A (en) * 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
US5623684A (en) * 1994-05-17 1997-04-22 Commquest Technologies, Inc. Application specific processor architecture comprising pre-designed reconfigurable application elements interconnected via a bus with high-level statements controlling configuration and data routing
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5748979A (en) * 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5819064A (en) * 1995-11-08 1998-10-06 President And Fellows Of Harvard College Hardware extraction technique for programmable reduced instruction set computers
JPH1011289A (ja) * 1996-06-19 1998-01-16 Mitsubishi Electric Corp 並列処理プロセッサにおける命令数拡張方法および並列処理プロセッサ

Similar Documents

Publication Publication Date Title
JP2000020305A5 (enExample)
CA2230694A1 (en) Self-timed pipelined datapath system and asynchronous signal control circuit
WO1999040522A3 (en) Digital signal processor using a reconfigurable array of macrocells
EP1416388A4 (en) INTEGRATED CIRCUIT DEVICE
EP1302848A3 (en) A microprocessor having a multiply operation
JPH10136149A5 (enExample)
EP1172730A3 (en) One-chip system large-scale integrated circuit including processor circuit and its pheripheral circuits
JPH01162967A (ja) 割込み処理方法及び装置
JP2001209534A5 (enExample)
EP2267596A3 (en) Processor core for processing instructions of different formats
JPS5937639U (ja) 工業用処理装置
WO2002029554A3 (en) Register move operations
JPH10269775A5 (enExample)
JP3904072B2 (ja) プログラマブル論理回路及びコンピュータシステム並びに回路の初期化方法
JPH1168495A5 (enExample)
US7133979B2 (en) Method of transferring data between a first device and a second device while manipulating at least one quantity in dependence on an address
JPH11161519A (ja) リセット装置
JP2968321B2 (ja) データ処理装置
JPS588366A (ja) メモリモジユ−ルシステム
JPS6037061A (ja) マイクロコンピユ−タ
JPH04264951A (ja) ディジタル信号処理装置
JPH0452248U (enExample)
JPS6452064U (enExample)
JPH0452250U (enExample)
JPS6452062U (enExample)