JP2000012616A - Method of mounting semiconductor device - Google Patents
Method of mounting semiconductor deviceInfo
- Publication number
- JP2000012616A JP2000012616A JP10174898A JP17489898A JP2000012616A JP 2000012616 A JP2000012616 A JP 2000012616A JP 10174898 A JP10174898 A JP 10174898A JP 17489898 A JP17489898 A JP 17489898A JP 2000012616 A JP2000012616 A JP 2000012616A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- thermosetting resin
- semiconductor chip
- sheet
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、突起電極（バン
プ）を有する裸の半導体素子（以下半導体チップとい
う）を、配線電極を有する回路基板上に装着する半導体
装置の実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device in which a bare semiconductor element (hereinafter, referred to as a semiconductor chip) having projecting electrodes (bumps) is mounted on a circuit board having wiring electrodes.
【０００２】[0002]
【従来の技術】従来、半導体チップ上のバンプ形成方法
として、ボールボンディング法による方法、及びその半
導体チップの回路基板への実装方法が米国特許第４６６
１１９２号明細書及び図面に示されている。この方法に
ついて、以下説明する。2. Description of the Related Art Conventionally, as a method for forming bumps on a semiconductor chip, a method using a ball bonding method and a method for mounting the semiconductor chip on a circuit board are disclosed in US Pat.
No. 1192 and in the drawings. This method will be described below.
【０００３】図１０（ａ）において、キャピラリー１５
の先端から出ているＡｕのワイヤ１６の先端に対し、放
電電極（トーチ）１７から数千ボルトの高電圧を印加す
る。これによってトーチ１７とワイヤ１６の先端に放電
電流が流れている間、ワイヤ１６は先端から高温とな
り、図１０（ｂ）に示したようにボール１８状になる。[0003] Referring to FIG.
A high voltage of several thousand volts is applied from the discharge electrode (torch) 17 to the tip of the Au wire 16 protruding from the tip. As a result, while the discharge current flows between the torch 17 and the distal end of the wire 16, the temperature of the wire 16 rises from the distal end, and becomes a ball 18 shape as shown in FIG. 10B.
【０００４】このワイヤ先端に形成されたボール１８を
キャピラリー１５によって、図１０（ｃ）に示したよう
に、半導体チップ１の電極パッド２上に固着し、バンプ
底部１９を形成した後、キャピラリー１５を上方へ引き
上げてワイヤ１６を少し引き出し、次いで、図１０
（ｄ）に示したように、そのワイヤをバンプ底部１９の
上方でルービング２０し、その端をバンプ底部１９へ固
着し、切断する。このようにしてバンプ３を形成する。[0004] As shown in FIG. 10 (c), the ball 18 formed at the tip of the wire is fixed on the electrode pad 2 of the semiconductor chip 1 to form a bump bottom 19, as shown in FIG. Is pulled upward to slightly pull out the wire 16, and then FIG.
As shown in (d), the wire is rubbed 20 above the bump bottom 19, and its end is fixed to the bump bottom 19 and cut. Thus, the bumps 3 are formed.
【０００５】次に、図１１（ａ）に示したように、バン
プ３が必要数形成された半導体チップ１を吸着治具２１
に吸着し、平坦面を有するステージ２２に押し付け、バ
ンプ先端レベルを揃える。さらに、図１１（ｂ）に示し
たように、別のステージ２３上に形成した厚さ一定の導
電性接着剤層２４にバンプ３を接触させ、導電性接着剤
を転写させる。[0005] Next, as shown in FIG. 11 (a), the semiconductor chip 1 on which the required number of bumps 3 are formed is attached to the suction jig 21.
, And pressed against the stage 22 having a flat surface to align the bump tip levels. Further, as shown in FIG. 11B, the bump 3 is brought into contact with a conductive adhesive layer 24 having a constant thickness formed on another stage 23 to transfer the conductive adhesive.
【０００６】そして、図１１（ｃ）に示したように、転
写された導電性接着剤４を有するバンプ３を回路基板５
の配線電極６に位置合わせして接触させ、導電性接着剤
４を硬化させることにより、半導体チップ１と回路基板
５との電気的接続を行う。Then, as shown in FIG. 11C, the bump 3 having the transferred conductive adhesive 4 is attached to the circuit board 5.
The semiconductor chip 1 and the circuit board 5 are electrically connected by aligning and contacting the wiring electrodes 6 of the semiconductor chip 1 and curing the conductive adhesive 4.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上記の
ような従来の方法では、半導体チップ１と回路基板５と
の電気的接続をバンプ３上に形成した導電性接着剤４を
介して行うものであるため、その導電性接着剤を硬化さ
せる際、現在、１２０℃で２時間加熱しているが、温度
が高くなると、回路基板と半導体チップとの熱膨張係数
の差によって電極接合部に熱歪がかかり、その結果、ク
ラックが発生するという問題があった。However, in the above-described conventional method, the electrical connection between the semiconductor chip 1 and the circuit board 5 is made via the conductive adhesive 4 formed on the bump 3. Therefore, when the conductive adhesive is cured, it is currently heated at 120 ° C. for 2 hours. However, when the temperature increases, a thermal strain is applied to the electrode joint due to a difference in thermal expansion coefficient between the circuit board and the semiconductor chip. As a result, there is a problem that cracks occur.
【０００８】本発明は、上記従来技術の問題点を解決す
るもので、半導体チップと回路基板との電極接合部にお
いて、熱歪によるクラックの発生を防止し、品質の高い
接合を得るようにした半導体装置の製造方法を提供する
ことを目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, in which cracks due to thermal strain are prevented from occurring at an electrode joint between a semiconductor chip and a circuit board, and a high-quality joint is obtained. It is an object to provide a method for manufacturing a semiconductor device.
【０００９】[0009]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置の実装方法は、回路基板の配
線電極と半導体チップのバンプ（以下突起電極という）
とを電気的に接続する際、半導体チップの一部と回路基
板との間を、まず、取り扱い易いシート状の熱硬化型樹
脂を用いて接着して機械的に固定した後、接着部の周囲
に液状の熱硬化型樹脂を充填、硬化して半導体チップの
回路形成面を封止するものである。In order to achieve the above object, a method of mounting a semiconductor device according to the present invention comprises a method of mounting a wiring electrode on a circuit board and a bump on a semiconductor chip (hereinafter referred to as a bump electrode).
When electrically connecting a part of the semiconductor chip and the circuit board, firstly, mechanically fix them by bonding them with a sheet-like thermosetting resin that is easy to handle, and then around the bonding part. Is filled with a liquid thermosetting resin and cured to seal the circuit forming surface of the semiconductor chip.
【００１０】そこで、請求項１に記載の本発明方法は、
配線電極を有する回路基板に対し、回路形成面に突起電
極を設けた半導体チップを装着するに際し、前記配線電
極と突起電極を位置合わせして電気的に接続するととも
に、前記半導体チップの略中央部分を前記回路基板の対
向する部分にシート状の熱硬化型樹脂で接着し、さら
に、接着したシート状の熱硬化型樹脂の周囲の前記半導
体チップと回路基板との隙間に液状の熱硬化型樹脂を注
入し、硬化して封止することを特徴とするものである。Therefore, the method of the present invention described in claim 1 is:
When mounting a semiconductor chip provided with a protruding electrode on a circuit forming surface to a circuit board having a wiring electrode, the wiring electrode and the protruding electrode are aligned and electrically connected, and a substantially central portion of the semiconductor chip is mounted. Is bonded to the opposing portion of the circuit board with a sheet-like thermosetting resin, and further, a liquid thermosetting resin is provided in a gap between the semiconductor chip and the circuit board around the bonded sheet-like thermosetting resin. Is injected, cured and sealed.
【００１１】また、請求項２に記載の本発明方法は、配
線電極を有する回路基板に対し、回路形成面に突起電極
を設けた半導体チップを装着するに際し、前記配線電極
と突起電極を位置合わせして電気的に接続するととも
に、前記半導体チップの周縁部を前記回路基板の対向す
る部分にシート状の熱硬化型樹脂で接着し、さらに、シ
ート状の熱硬化型樹脂で囲まれた部分の前記半導体チッ
プと回路基板との隙間に、前記回路基板に設けた孔から
液状の熱硬化型樹脂を注入し、硬化して封止することを
特徴とするものである。According to a second aspect of the present invention, when a semiconductor chip having a protruding electrode provided on a circuit forming surface is mounted on a circuit board having a wiring electrode, the wiring electrode and the protruding electrode are aligned. And electrically connect the peripheral portion of the semiconductor chip to a facing portion of the circuit board with a sheet-like thermosetting resin, and further, a portion surrounded by the sheet-like thermosetting resin. A liquid thermosetting resin is injected into a gap between the semiconductor chip and the circuit board from a hole provided in the circuit board, and is cured and sealed.
【００１２】そして、配線電極と突起電極との電気的接
続は導電性接着剤により行い、その導電性接着剤とシー
ト状の熱硬化型樹脂を同時に加熱硬化することができ
る。The electrical connection between the wiring electrode and the protruding electrode is made by a conductive adhesive, and the conductive adhesive and the sheet-like thermosetting resin can be simultaneously heated and cured.
【００１３】上記構成によれば、シート状の熱硬化型樹
脂で半導体チップと回路基板が確実に固着されるので、
回路基板と半導体チップとの熱膨張係数の差による反り
の発生を抑制し、電極接合部のクラックの発生を防止す
ることができ、信頼性の高い半導体装置の実装が得られ
る。また、シート状の熱硬化型樹脂は、供給量が安定
し、かつ時間の経過で濡れ広がって電極部を汚すことが
ない。また、液状の熱硬化型樹脂による封止で、半導体
チップの耐湿および耐熱信頼性を向上することができ
る。According to the above configuration, the semiconductor chip and the circuit board are securely fixed by the sheet-like thermosetting resin.
It is possible to suppress the occurrence of warpage due to the difference in the coefficient of thermal expansion between the circuit board and the semiconductor chip, to prevent the occurrence of cracks at the electrode junction, and to obtain a highly reliable semiconductor device. In addition, the supply amount of the sheet-shaped thermosetting resin is stable, and the sheet-shaped thermosetting resin does not spread over time and stain the electrode portion. Further, the sealing with the liquid thermosetting resin can improve the humidity resistance and the heat resistance of the semiconductor chip.
【００１４】なお、回路基板は、シート状の熱硬化型樹
脂が接着される部分に、導体ランドまたはレジスト等の
樹脂膜からなる専用の接着領域を設けてもよい。この専
用の接着領域は、回路基板の接着面を平坦にし、気泡の
巻き込みをなくして密着強度を上げ、したがって、気泡
の熱膨張がないので、耐熱信頼性をさらに高める。ま
た、専用の接着領域を複数の小領域で形成してもよい。
この場合、固着された半導体チップに対し、応力を分散
する作用がある。The circuit board may be provided with a dedicated bonding area made of a resin film such as a conductor land or a resist at a portion where the sheet-like thermosetting resin is bonded. This dedicated bonding area flattens the bonding surface of the circuit board, eliminates the entrapment of air bubbles, and enhances the adhesion strength, and thus eliminates the thermal expansion of the air bubbles, thereby further improving the heat resistance. Further, a dedicated bonding area may be formed by a plurality of small areas.
In this case, there is an effect of dispersing the stress on the fixed semiconductor chip.
【００１５】専用の接着領域を、菱形等の四角形や楕円
等の円形で形成すると、液状の熱硬化型樹脂を充填する
際、樹脂がスムーズに流れ、気泡の発生もなくなる。専
用の接着領域は、その専用領域全体が導体層または樹脂
膜で形成され、あるいはその外径のみが導体または樹脂
で縁取られていてもよい。If the exclusive bonding area is formed in a square such as a rhombus or a circle such as an ellipse, the resin flows smoothly and no bubbles are generated when the liquid thermosetting resin is filled. The dedicated bonding region may be formed entirely of a conductor layer or a resin film, or only the outer diameter thereof may be bordered by a conductor or a resin.
【００１６】[0016]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１７】（実施の形態１）図１は、本発明の実施の
形態１における半導体チップを回路基板へ実装した状態
を示したものである。図１において、１は半導体チッ
プ、２は電極パッド、３は電極パッド２上に形成された
突起電極で、例えば、図１０で示した方法で形成され
る。４は導電性接着剤で、図１１に示したようにして突
起電極３に転写させたものである。５は回路基板、６は
回路基板５上に形成された配線電極、７は半導体チップ
１と回路基板５とを機械的に接着するシート状の熱硬化
型樹脂、８は、シート状の熱硬化型樹脂７および電極部
分を包み込むようにして、半導体チップ１と回路基板５
との隙間に注入し、硬化した液状の熱硬化型樹脂であ
る。半導体チップ１の回路形成面は液状の熱硬化型樹脂
８により封止されている。(Embodiment 1) FIG. 1 shows a state in which a semiconductor chip according to Embodiment 1 of the present invention is mounted on a circuit board. In FIG. 1, reference numeral 1 denotes a semiconductor chip, 2 denotes an electrode pad, and 3 denotes a projection electrode formed on the electrode pad 2, which is formed, for example, by the method shown in FIG. Reference numeral 4 denotes a conductive adhesive which has been transferred to the bump electrodes 3 as shown in FIG. 5 is a circuit board, 6 is a wiring electrode formed on the circuit board 5, 7 is a sheet-like thermosetting resin for mechanically bonding the semiconductor chip 1 and the circuit board 5, and 8 is a sheet-like thermosetting resin. The semiconductor chip 1 and the circuit board 5 are wrapped around the mold resin 7 and the electrode portions.
Is a liquid thermosetting resin that has been injected and cured in the gap. The circuit forming surface of the semiconductor chip 1 is sealed with a liquid thermosetting resin 8.
【００１８】次に、本実施の形態１における半導体装置
の実装方法について説明する。まず、突起電極３に導電
性接着剤４を付着させた半導体チップ１を用意する。次
に、図２（ａ）に示したように、回路基板５の半導体チ
ップ装着領域の略中央部にシート状の熱硬化型樹脂７を
仮接着する。または図２（ｂ）に示したように、このシ
ート状の熱硬化型樹脂７を、半導体チップ１の中央部に
仮接着してもよい。Next, a method of mounting the semiconductor device according to the first embodiment will be described. First, the semiconductor chip 1 in which the conductive adhesive 4 is adhered to the bump electrode 3 is prepared. Next, as shown in FIG. 2A, a sheet-like thermosetting resin 7 is temporarily bonded to substantially the center of the semiconductor chip mounting region of the circuit board 5. Alternatively, as shown in FIG. 2B, the sheet-shaped thermosetting resin 7 may be temporarily bonded to the center of the semiconductor chip 1.
【００１９】次いで、図２（ｃ）に示したように、半導
体チップ１の導電性接着剤４が転写された突起電極３を
回路基板５の配線電極６に位置合わせして接触させ、熱
及び圧力を同時に加えて電極部の導電性接着剤４とシー
ト状の熱硬化型樹脂７とを同時に硬化し、電気的接続と
ともに、機械的固着を達成する。Next, as shown in FIG. 2C, the projecting electrode 3 to which the conductive adhesive 4 of the semiconductor chip 1 has been transferred is aligned with and brought into contact with the wiring electrode 6 of the circuit board 5, and heat and The conductive adhesive 4 and the sheet-like thermosetting resin 7 at the electrode portion are simultaneously cured by applying pressure to achieve electrical connection and mechanical fixation.
【００２０】さらに、図２（ｄ）に示したように、接合
後の半導体チップ１と回路基板５との間のシート状の熱
硬化型樹脂７の周辺に、樹脂注入機２５を使用して液状
の熱硬化型樹脂８を注入し、熱を加えて硬化させる。Further, as shown in FIG. 2D, a resin injection machine 25 is used around the sheet-like thermosetting resin 7 between the bonded semiconductor chip 1 and the circuit board 5. The liquid thermosetting resin 8 is injected and heated to cure.
【００２１】このような本実施の形態１における半導体
装置の実装方法によれば、電極接合部の導電性接着剤４
とシート状の熱硬化型樹脂７とを同時かつ短時間（１８
０℃、１２０秒）で硬化することができるとともに、突
起電極３の数が少ない半導体チップ１の接合において
も、シート状の熱硬化型樹脂７で回路基板５と半導体チ
ップ１とを強い機械的強度で接着することができ、回路
基板５の反り等に対しても、信頼性の高い電極接合が得
られ、さらに、液状の熱硬化型樹脂８を充填することに
よって半導体チップ１の回路形成面を十分にシールする
ことができるので、半導体装置としての信頼性を向上す
ることができる。また、半導体チップ１を回路基板５に
接着する熱硬化型樹脂７として、シート状の樹脂を使用
するので、供給量が安定し、かつ時間的経過で濡れ広が
って回路基板５上の配線電極６を汚すこともない。絶縁
性の熱硬化型樹脂としては、エポキシ系樹脂やシリコー
ン系樹脂が使用できる。According to the method of mounting the semiconductor device according to the first embodiment, the conductive adhesive 4 at the electrode joint is used.
And the sheet-like thermosetting resin 7 simultaneously and for a short time (18
(0 ° C., 120 seconds), and also in bonding the semiconductor chip 1 having a small number of protruding electrodes 3, the circuit board 5 and the semiconductor chip 1 are strongly mechanically bonded with the sheet-like thermosetting resin 7. The bonding can be performed with high strength, and highly reliable electrode bonding can be obtained even with respect to warpage of the circuit board 5. Further, by filling the liquid thermosetting resin 8, the circuit forming surface of the semiconductor chip 1 is formed. Can be sufficiently sealed, so that the reliability as a semiconductor device can be improved. Further, since a sheet-like resin is used as the thermosetting resin 7 for bonding the semiconductor chip 1 to the circuit board 5, the supply amount is stable, and the wiring electrode 6 on the circuit board 5 spreads over time by spreading. It does not pollute. As the insulating thermosetting resin, an epoxy resin or a silicone resin can be used.
【００２２】回路基板５は、シート状の熱硬化型樹脂７
が接着される部分に、図３に示したように、予め導体ラ
ンドまたはレジスト等の樹脂膜からなる専用の接着領域
１０を設けてもよい。この専用の接着領域１０は、回路
基板５上の接着面を平坦にしてシート状の熱硬化型樹脂
７の密着性を高めることができ、例えば、図４に示した
ような配線１１がある場合の配線間の凹部に気泡を巻き
込む可能性がなくなり、熱印加時の気泡の膨張で密着強
度が低下するような信頼性の低下はない。The circuit board 5 is made of a sheet-like thermosetting resin 7.
As shown in FIG. 3, a dedicated bonding area 10 made of a resin film such as a conductor land or a resist may be provided in advance at the portion where the is bonded. The dedicated bonding area 10 can improve the adhesion of the sheet-like thermosetting resin 7 by flattening the bonding surface on the circuit board 5. For example, when the wiring 11 shown in FIG. There is no possibility that air bubbles may be trapped in the recesses between the wirings, and there is no reduction in reliability such that the adhesion strength is reduced due to expansion of the air bubbles when heat is applied.
【００２３】専用の接着領域１０は、図５に示したよう
に、菱形にし、液状の熱硬化型樹脂を注入、充填する
際、樹脂が半導体チップ１と回路基板５の隙間を毛細管
現象で接着領域の長い方向にスムーズに浸入していくよ
うにすれば、シート状の熱硬化型樹脂７の後部によどみ
や気泡の発生がなくなる。専用の接着領域１０の形状と
しては、外に図７（ａ）〜（ｈ）で示したような各種の
ものが考えられる。また、専用の接着領域１０は、図７
（ｉ）のように、その専用領域全体が導体層または樹脂
膜で形成されてもよいし、あるいは図７（ｊ）のよう
に、その外径のみが導体または樹脂で縁取られていても
よい。As shown in FIG. 5, a dedicated bonding area 10 is formed in a rhombus shape, and when a liquid thermosetting resin is injected and filled, the resin bonds a gap between the semiconductor chip 1 and the circuit board 5 by a capillary phenomenon. By smoothly penetrating in the long direction of the region, stagnation and bubbles are not generated at the rear part of the sheet-like thermosetting resin 7. Various shapes such as those shown in FIGS. 7A to 7H can be considered as the shape of the dedicated bonding region 10. In addition, the dedicated bonding area 10 is provided in FIG.
As shown in (i), the entire dedicated area may be formed of a conductor layer or a resin film, or only the outer diameter thereof may be bordered by a conductor or a resin as shown in FIG. 7 (j). .
【００２４】さらに、図６に示したように、専用の接着
領域１０を複数の小領域１０ａ，１０ｂ，１０ｃのよう
に形成してもよい。この場合は、シート状の熱硬化型樹
脂７もこれに対応して複数部分７ａ，７ｂ，７ｃに分割
する。このようにすると、固着後の半導体チップ１に対
し、応力を分散させることができる。Further, as shown in FIG. 6, a dedicated bonding area 10 may be formed like a plurality of small areas 10a, 10b, 10c. In this case, the sheet-like thermosetting resin 7 is also divided into a plurality of portions 7a, 7b, 7c correspondingly. In this way, the stress can be dispersed in the semiconductor chip 1 after being fixed.
【００２５】（実施の形態２）図８は、本発明の実施の
形態２における半導体チップを回路基板へ実装した状態
を示したものである。図８において、図１と同一名称部
分には同一符号を付してある。ここで、実施の形態１と
異なるところは、半導体チップ１の周縁部と、回路基板
５の対向する部分とをシート状の熱硬化型樹脂７で接着
し、さらに、シート状の熱硬化型樹脂７で囲まれた部分
の半導体チップ１と回路基板５との隙間に、回路基板５
に設けた孔９から液状の熱硬化型樹脂８を注入し、硬化
して封止する点である。(Embodiment 2) FIG. 8 shows a state in which a semiconductor chip according to Embodiment 2 of the present invention is mounted on a circuit board. 8, the same reference numerals are given to the same components as those in FIG. Here, the difference from the first embodiment is that the peripheral portion of the semiconductor chip 1 and the opposing portion of the circuit board 5 are bonded with a sheet-like thermosetting resin 7, and further, the sheet-like thermosetting resin In the gap between the semiconductor chip 1 and the circuit board 5 in the portion surrounded by 7, the circuit board 5
The point is that the liquid thermosetting resin 8 is injected from the hole 9 provided in the above, and is cured and sealed.
【００２６】次に、本実施の形態２における半導体装置
の実装方法について説明する。まず、突起電極３に導電
性接着剤４を付着させた半導体チップ１を用意する。次
に、図９（ａ）に示したように、回路基板５の、半導体
チップ１の周縁部が対向する部分に、シート状の熱硬化
型樹脂７を仮接着する。Next, a method of mounting the semiconductor device according to the second embodiment will be described. First, the semiconductor chip 1 in which the conductive adhesive 4 is adhered to the bump electrode 3 is prepared. Next, as shown in FIG. 9A, a sheet-like thermosetting resin 7 is temporarily bonded to a portion of the circuit board 5 where the peripheral edge of the semiconductor chip 1 faces.
【００２７】次いで、図９（ｂ）に示したように、半導
体チップ１の導電性接着剤４が転写された突起電極３を
回路基板５の配線電極６に位置合わせして接触させ、熱
及び圧力を同時に加えて電極部の導電性接着剤４とシー
ト状の熱硬化型樹脂７とを同時に硬化し、電気的接続と
ともに、機械的固着を達成する。Next, as shown in FIG. 9B, the protruding electrode 3 to which the conductive adhesive 4 of the semiconductor chip 1 has been transferred is aligned and brought into contact with the wiring electrode 6 of the circuit board 5, and heat and heat are applied thereto. The conductive adhesive 4 and the sheet-like thermosetting resin 7 at the electrode portion are simultaneously cured by applying pressure to achieve electrical connection and mechanical fixation.
【００２８】さらに、接着後のシート状の熱硬化型樹脂
７で囲まれた部分の半導体チップ１と回路基板５との隙
間に、回路基板５に設けた孔９から樹脂注入機２５を使
用して液状の熱硬化型樹脂８を注入し、熱を加えて硬化
させる。Further, a resin injecting machine 25 is used through a hole 9 formed in the circuit board 5 in a gap between the semiconductor chip 1 and the circuit board 5 in a portion surrounded by the sheet-like thermosetting resin 7 after bonding. Then, a liquid thermosetting resin 8 is injected and heated to be cured.
【００２９】このような本実施の形態２における半導体
装置の実装方法によれば、実施の形態１と同様に、電極
接合部の導電性接着剤４とシート状の熱硬化型樹脂７と
を同時かつ短時間で硬化することができるとともに、突
起電極３の数が少ない半導体チップ１の接合において
も、シート状の熱硬化型樹脂７で回路基板５と半導体チ
ップ１とを強い機械的強度で接着することができ、回路
基板５の反り等に対しても、信頼性の高い電極整合が得
られ、さらに、液状の熱硬化型樹脂８を充填することに
よって半導体チップ１の回路形成面を十分にシールする
ことができるので、半導体装置としての信頼性を向上す
ることができる。また、半導体チップ１を回路基板５に
接着する熱硬化型樹脂７として、シート状の樹脂を使用
するので、供給量が安定し、かつ時間的経過で濡れ広が
って回路基板５上の配線電極６を汚すこともない。According to the mounting method of the semiconductor device according to the second embodiment, similarly to the first embodiment, the conductive adhesive 4 at the electrode joint portion and the sheet-like thermosetting resin 7 are simultaneously formed. In addition, the circuit board 5 and the semiconductor chip 1 can be hardened in a short time, and the circuit board 5 and the semiconductor chip 1 are bonded to each other by the sheet-like thermosetting resin 7 with high mechanical strength even when the semiconductor chip 1 having a small number of projecting electrodes 3 is joined. A highly reliable electrode alignment can be obtained even with respect to the warpage of the circuit board 5 and the like, and the circuit formation surface of the semiconductor chip 1 can be sufficiently filled by filling the liquid thermosetting resin 8. Since sealing can be performed, reliability as a semiconductor device can be improved. Further, since a sheet-like resin is used as the thermosetting resin 7 for bonding the semiconductor chip 1 to the circuit board 5, the supply amount is stable, and the wiring electrode 6 on the circuit board 5 spreads over time by spreading. It does not pollute.
【００３０】[0030]
【発明の効果】以上説明したように、本発明によれば、
回路基板の配線電極と半導体チップの突起電極とを電気
的に接続する際、半導体チップの一部と回路基板との間
を、まず、取り扱い易いシート状の熱硬化型樹脂を用い
て接着して機械的に固着した後、その固着部の周囲ある
いは固着部に囲まれた半導体チップと回路基板との隙間
に液状の熱硬化型樹脂を充填して硬化するので、電極部
の接合強度を高め、基板（熱膨張係数７０ｐｐｍ／℃）
と半導体チップ（熱膨張係数３ｐｐｍ／℃）の熱膨張係
数差による電極接合部への熱歪み（応力）に対して、品
質の高い接合を得ることができる。さらに半導体チップ
の回路形成面を液状の熱硬化型樹脂で封止し、外部と遮
断するので、半導体チップの信頼性を高めることができ
るという効果を奏する。As described above, according to the present invention,
When electrically connecting the wiring electrodes of the circuit board and the protruding electrodes of the semiconductor chip, a part of the semiconductor chip and the circuit board are first adhered using a sheet-like thermosetting resin which is easy to handle. After being mechanically fixed, a liquid thermosetting resin is filled in the gap between the semiconductor chip and the circuit board surrounded by the fixed portion or surrounded by the fixed portion and hardened, so that the bonding strength of the electrode portion is increased, Substrate (coefficient of thermal expansion 70 ppm / ° C)
High-quality bonding can be obtained with respect to thermal distortion (stress) at the electrode bonding portion due to the difference in thermal expansion coefficient between the semiconductor chip and the semiconductor chip (thermal expansion coefficient: 3 ppm / ° C.). Further, since the circuit forming surface of the semiconductor chip is sealed with a liquid thermosetting resin and shielded from the outside, there is an effect that the reliability of the semiconductor chip can be improved.
【図１】本発明の実施の形態１における半導体チップを
回路基板へ実装した状態を示す断面図FIG. 1 is a sectional view showing a state where a semiconductor chip according to a first embodiment of the present invention is mounted on a circuit board;
【図２】本発明の実施の形態１における実装方法の工程
断面図FIG. 2 is a process sectional view of the mounting method according to the first embodiment of the present invention;
【図３】専用の接着領域を設けた場合を示す図FIG. 3 is a diagram showing a case where a dedicated bonding area is provided.
【図４】専用の接着領域を設けない場合の問題点を示す
図FIG. 4 is a diagram showing a problem when a dedicated bonding area is not provided.
【図５】専用の接着領域の形状を菱形とした場合を示す
図FIG. 5 is a diagram showing a case where the shape of a dedicated bonding area is a rhombus;
【図６】専用の接着領域を複数の小領域に形成した場合
を示す図FIG. 6 is a diagram showing a case where a dedicated bonding area is formed in a plurality of small areas.
【図７】専用の接着領域の他の各種形状例を示す図FIG. 7 is a view showing another example of various shapes of a dedicated bonding area.
【図８】本発明の実施の形態２における半導体チップを
回路基板へ実装した状態を示す断面図FIG. 8 is a sectional view showing a state in which the semiconductor chip according to the second embodiment of the present invention is mounted on a circuit board.
【図９】本発明の実施の形態２における実装方法の工程
断面図FIG. 9 is a process sectional view of the mounting method in the second embodiment of the present invention;
【図１０】従来の半導体チップ上のバンプ形成法を示す
図FIG. 10 is a diagram showing a conventional bump forming method on a semiconductor chip.
【図１１】従来のバンプを有する半導体チップを回路基
板へ実装する工程断面図FIG. 11 is a sectional view showing a process of mounting a conventional semiconductor chip having bumps on a circuit board.
１ 半導体チップ ２ 電極パッド ３ 突起電極（バンプ） ４ 導電性接着剤 ５ 回路基板 ６ 配線電極 ７ シート状の熱硬化型樹脂 ８ 液状の熱硬化型樹脂 ９ 孔 １０ 専用の接着領域 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode pad 3 Protruding electrode (bump) 4 Conductive adhesive 5 Circuit board 6 Wiring electrode 7 Sheet-shaped thermosetting resin 8 Liquid thermosetting resin 9 Hole 10 Special bonding area
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M105 AA01 AA11 AA27 BB07 BB17 FF01 GG17 GG18 GG19 4M109 AA01 BA04 CA02 CA04 DA06 EA01 5F061 AA01 BA04 CA02 CA04 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M105 AA01 AA11 AA27 BB07 BB17 FF01 GG17 GG18 GG19 4M109 AA01 BA04 CA02 CA04 DA06 EA01 5F061 AA01 BA04 CA02 CA04
Claims (10)
形成面に突起電極を設けた半導体チップを装着するに際
し、前記配線電極と突起電極を位置合わせして電気的に
接続するとともに、前記半導体チップの略中央部分を前
記回路基板の対向する部分にシート状の熱硬化型樹脂で
接着し、さらに、接着したシート状の熱硬化型樹脂の周
囲の前記半導体チップと回路基板との隙間に液状の熱硬
化型樹脂を注入し、硬化して封止することを特徴とする
半導体装置の実装方法。When a semiconductor chip provided with a protruding electrode on a circuit forming surface is mounted on a circuit board having a wiring electrode, the wiring electrode and the protruding electrode are positioned and electrically connected, and the semiconductor is mounted. A substantially central portion of the chip is bonded to a facing portion of the circuit board with a sheet-like thermosetting resin, and a liquid is applied to a gap between the semiconductor chip and the circuit board around the bonded sheet-like thermosetting resin. A method for mounting a semiconductor device, comprising: injecting a thermosetting resin, and curing and sealing the same.
形成面に突起電極を設けた半導体チップを装着するに際
し、前記配線電極と突起電極を位置合わせして電気的に
接続するとともに、前記半導体チップの周縁部を前記回
路基板の対向する部分にシート状の熱硬化型樹脂で接着
し、さらに、シート状の熱硬化型樹脂で囲まれた部分の
前記半導体チップと回路基板との隙間に、前記回路基板
に設けた孔から液状の熱硬化型樹脂を注入し、硬化して
封止することを特徴とする半導体装置の実装方法。2. When a semiconductor chip provided with a protruding electrode on a circuit forming surface is mounted on a circuit board having a wiring electrode, the wiring electrode and the protruding electrode are aligned and electrically connected, and The peripheral portion of the chip is adhered to the opposing portion of the circuit board with a sheet-like thermosetting resin, and further, in the gap between the semiconductor chip and the circuit board in the portion surrounded by the sheet-like thermosetting resin, A method for mounting a semiconductor device, comprising: injecting a liquid thermosetting resin through a hole provided in the circuit board, and curing and sealing the resin.
電性接着剤により行うことを特徴とする請求項１または
請求項２記載の半導体装置の実装方法。3. The method according to claim 1, wherein the electrical connection between the wiring electrode and the protruding electrode is made by a conductive adhesive.
を同時に加熱硬化することを特徴とする請求項３記載の
半導体装置の実装方法。4. The method for mounting a semiconductor device according to claim 3, wherein the conductive adhesive and the sheet-like thermosetting resin are simultaneously heated and cured.
接着される部分に、導体ランドまたはレジスト等の樹脂
膜からなる専用の接着領域を有することを特徴とする請
求項１記載の半導体装置の実装方法。5. The semiconductor according to claim 1, wherein the circuit board has a dedicated bonding region made of a resin film such as a conductor land or a resist at a portion where the sheet-shaped thermosetting resin is bonded. How to mount the device.
らなる専用の接着領域は、複数の小領域から形成されて
いることを特徴とする請求項５記載の半導体装置の実装
方法。6. The method of mounting a semiconductor device according to claim 5, wherein the exclusive bonding region made of a resin film such as a conductor land or a resist is formed from a plurality of small regions.
ることを特徴とする請求項５または請求項６記載の半導
体装置の実装方法。7. The semiconductor device mounting method according to claim 5, wherein the exclusive bonding area is a square such as a rhombus.
ことを特徴とする請求項５または請求項６記載の半導体
装置の実装方法。8. The method of mounting a semiconductor device according to claim 5, wherein the dedicated bonding area is a circle such as an ellipse.
導体層または樹脂膜で形成されていることを特徴とする
請求項５ないし請求項８のいずれか１項に記載の半導体
装置の実装方法。9. The mounting of the semiconductor device according to claim 5, wherein the exclusive bonding region is formed entirely of a conductive layer or a resin film. Method.
体または樹脂で縁取られていることを特徴とする請求項
５ないし請求項８のいずれか１項に記載の半導体装置の
実装方法。10. The method according to claim 5, wherein only the outer diameter of the dedicated adhesive region is bordered by a conductor or a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17489898A JP3525331B2 (en) | 1998-06-22 | 1998-06-22 | Semiconductor chip mounting substrate and semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17489898A JP3525331B2 (en) | 1998-06-22 | 1998-06-22 | Semiconductor chip mounting substrate and semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000012616A true JP2000012616A (en) | 2000-01-14 |
| JP3525331B2 JP3525331B2 (en) | 2004-05-10 |
Family
ID=15986625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17489898A Expired - Fee Related JP3525331B2 (en) | 1998-06-22 | 1998-06-22 | Semiconductor chip mounting substrate and semiconductor device mounting method |
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| Country | Link |
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| JP (1) | JP3525331B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006019599A (en) * | 2004-07-05 | 2006-01-19 | Matsushita Electric Ind Co Ltd | Semiconductor device, its manufacturing method, and its packaging method |
| JP2006253277A (en) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Semiconductor device for module, module using the same, and module manufacturing method |
| US10607964B2 (en) | 2015-05-29 | 2020-03-31 | Toshiba Memory Corporation | Semiconductor device |
-
1998
- 1998-06-22 JP JP17489898A patent/JP3525331B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006019599A (en) * | 2004-07-05 | 2006-01-19 | Matsushita Electric Ind Co Ltd | Semiconductor device, its manufacturing method, and its packaging method |
| JP4511266B2 (en) * | 2004-07-05 | 2010-07-28 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006253277A (en) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Semiconductor device for module, module using the same, and module manufacturing method |
| US10607964B2 (en) | 2015-05-29 | 2020-03-31 | Toshiba Memory Corporation | Semiconductor device |
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| JP3525331B2 (en) | 2004-05-10 |
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