JPH08153752A - Flip chip mounting method - Google Patents
Flip chip mounting methodInfo
- Publication number
- JPH08153752A JPH08153752A JP29285194A JP29285194A JPH08153752A JP H08153752 A JPH08153752 A JP H08153752A JP 29285194 A JP29285194 A JP 29285194A JP 29285194 A JP29285194 A JP 29285194A JP H08153752 A JPH08153752 A JP H08153752A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- sealing resin
- resin
- supplying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＳＩ等の半導体素子
を回路基板上に搭載するフリップチップ実装方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting method for mounting a semiconductor element such as an LSI on a circuit board.
【０００２】[0002]
【従来の技術】近年、電子機器の小型化、低価格化に伴
い簡略化した半導体素子の高密度実装が増えてきてい
る。このようなＬＳＩ等の半導体素子を回路基板に実装
する方法として、フリップチップ方式がある。2. Description of the Related Art In recent years, high-density mounting of simplified semiconductor elements has been increasing with the downsizing and cost reduction of electronic devices. There is a flip chip method as a method of mounting such a semiconductor element such as an LSI on a circuit board.
【０００３】これは、複数のバンプ電極を備えた半導体
素子をフェイスダウン方式で回路基板に接続する方法で
ある。This is a method of connecting a semiconductor element having a plurality of bump electrodes to a circuit board by a face-down method.
【０００４】図３に従来の方法で半導体素子６を回路基
板１上に実装したフリップチップ実装構造の断面図を示
す。ここで、７は半導体素子６のパッド上に形成された
バンプ電極であり、回路基板１上の実装用パッド３と接
続されている。４は半導体素子６と回路基板１を接続さ
せた状態で固定してしまうための接着剤であり、光硬化
性のものや、熱硬化性の樹脂が用いられる。FIG. 3 shows a sectional view of a flip-chip mounting structure in which the semiconductor element 6 is mounted on the circuit board 1 by a conventional method. Here, 7 is a bump electrode formed on the pad of the semiconductor element 6, and is connected to the mounting pad 3 on the circuit board 1. Reference numeral 4 denotes an adhesive for fixing the semiconductor element 6 and the circuit board 1 in a connected state, and a photo-curable or thermosetting resin is used.
【０００５】図３に示す構造のように半導体素子６をフ
リップチップ実装する方法は、特開平４−８２２４１号
公報に示されている。すなわち、回路基板１上の半導体
素子６が固定される領域（回路基板１上の実装用パッド
３も含む）に接着用樹脂４をスクリーン印刷により塗布
する。樹脂の供給方法については、この他にもディスペ
ンサー等により半導体素子６が固定される領域の中央に
のみ供給する方法も公知となっている（実装用パッド３
には供給しない）。次に、半導体素子６のバンプ電極７
と回路基板１上の実装用パッド３とを位置合わせし、半
導体素子６を回路基板１上に加圧圧接し硬化する。この
時、半導体素子６のバンプ電極７と回路基板１上の実装
用パッド３とは、その間に存在していた接着用樹脂４が
押し出されて電気的接続が可能となる。A method of flip-chip mounting the semiconductor element 6 having the structure shown in FIG. 3 is disclosed in Japanese Patent Application Laid-Open No. 4-82241. That is, the adhesive resin 4 is applied by screen printing to a region on the circuit board 1 where the semiconductor element 6 is fixed (including the mounting pad 3 on the circuit board 1). As for the method of supplying the resin, a method of supplying the resin only to the center of the region where the semiconductor element 6 is fixed by a dispenser or the like is also known (mounting pad 3).
Not supplied to). Next, the bump electrode 7 of the semiconductor element 6
And the mounting pad 3 on the circuit board 1 are aligned with each other, and the semiconductor element 6 is pressed and pressed onto the circuit board 1 to be cured. At this time, the bump electrodes 7 of the semiconductor element 6 and the mounting pads 3 on the circuit board 1 can be electrically connected by pushing out the adhesive resin 4 existing between them.
【０００６】[0006]
【発明が解決しようとする課題】上述したような従来の
フリップチップ実装方法において、その信頼性および歩
留まりを高くするためには、半導体素子のバンプ電極と
回路基板上の実装用パッドとの接合部周辺のボイド（接
着用樹脂の未充填部）の発生有無が重要なファクターに
なる。In the conventional flip-chip mounting method as described above, in order to increase the reliability and the yield, the bonding portion between the bump electrode of the semiconductor element and the mounting pad on the circuit board is required. The presence or absence of voids (non-filled portion of the adhesive resin) in the periphery is an important factor.
【０００７】ボイドの発生場所が接合部近辺に生じた場
合、接着用樹脂の接着力が接合部で弱くなり熱等のスト
レスに対してその接合が維持できなくなり、結果的に断
線してしまう恐れがある。When a void is generated near the joint, the adhesive force of the adhesive resin is weakened at the joint and the joint cannot be maintained against stress such as heat, resulting in disconnection. There is.
【０００８】また、ボイドが発生している部分では実装
基板が高温、高湿にさらされた場合、樹脂の存在がない
ためにその種類によっては回路基板の不純物イオンの格
好の通り道となり、Ｃ１- 等の影響により半導体素子の
Ａｌパッドを腐食させ、半導体素子を破壊する恐れがあ
る。Further, if the mounting substrate at a portion where the void is generated is exposed high temperature, a high humidity becomes a path of looking impurity ions of the circuit board by its kind for no presence of the resin, C1 - There is a risk that the Al pad of the semiconductor element will be corroded by the influence of the above, and the semiconductor element will be destroyed.
【０００９】特に、回路基板としてプリント配線板を用
いる場合、実装用パッド以外の部分は配線の保護と絶縁
の確保のために絶縁性のソルダーレジストがコートされ
ている。このため回路基板の実装用パッドはソルダーレ
ジストの溝の底に存在する形になる。In particular, when a printed wiring board is used as the circuit board, an insulating solder resist is coated on portions other than the mounting pads to protect the wiring and ensure insulation. For this reason, the mounting pad of the circuit board comes to exist at the bottom of the groove of the solder resist.
【００１０】特開平４−８２２４１号公報に示されたよ
うな接着用樹脂供給方法では、塗布の際そのエッジ部に
ボイドを生じるという問題を有している。The adhesive resin supply method as disclosed in Japanese Patent Laid-Open No. 4-82241 has a problem that a void is generated at the edge portion during coating.
【００１１】また、公知となっている中央にのみ樹脂を
供給する方法においても、半導体素子が加圧され接着用
樹脂が押し広がるときこのソルダーレジストの溝への流
れ込みが悪く、溝内に存在する接合部周辺にボイドが発
生するという問題を有している。Also in the known method of supplying the resin only to the center, when the semiconductor element is pressed and the adhesive resin is spread out, the solder resist does not flow into the groove well and exists in the groove. There is a problem that a void is generated around the joint.
【００１２】[0012]
【課題を解決するための手段】本発明のフリップチップ
実装方法は、回路基板を覆う絶縁膜に形成され底に実装
用パッドが配設された溝に封止樹脂ａを供給する第１の
供給工程と、この第１の供給工程の次に前記封止樹脂ａ
を真空脱泡する脱泡工程と、この脱泡工程の次に前記回
路基板上の半導体素子の実装部中央に封止樹脂ｂを供給
する第２の供給工程と、前記半導体素子のバンプと前記
実装用パッドとを位置合わせして前記半導体素子を前記
回路基板に押し付けて加熱し前記封止樹脂ａ、ｂを硬化
させる硬化工程とを有する。According to the flip-chip mounting method of the present invention, the first supply is performed by supplying the sealing resin a to the groove formed on the insulating film covering the circuit board and having the mounting pad on the bottom. Process, and the sealing resin a after the first supplying process.
A defoaming step of vacuum defoaming, a second supplying step of supplying a sealing resin b to the center of the mounting portion of the semiconductor element on the circuit board, and a bump of the semiconductor element A curing step of aligning the mounting pads with each other and pressing the semiconductor element against the circuit board to heat it to cure the sealing resins a and b.
【００１３】本発明のフリップチップ実装方法は、回路
基板を覆う絶縁膜に形成され底に実装用パッドが配設さ
れた溝に封止樹脂ａを供給する第１の供給工程と、この
第１の供給工程の次に前記封止樹脂ａに超音波振動を与
える脱泡工程と、この脱泡工程の次に前記回路基板上の
半導体素子の実装部中央に封止樹脂ｂを供給する第２の
供給工程と、前記半導体素子のバンプと前記実装用パッ
ドとを位置合わせして前記半導体素子を前記回路基板に
押し付けて加熱し前記樹脂封止ａ、ｂを硬化させる硬化
工程とを有する。The flip-chip mounting method of the present invention includes a first supplying step of supplying the sealing resin a to the groove formed in the insulating film covering the circuit board and having the mounting pad on the bottom, and the first supplying step. And a defoaming step of applying ultrasonic vibration to the sealing resin a, and a second step of supplying the sealing resin b to the center of the mounting portion of the semiconductor element on the circuit board after the defoaming step. And a curing step of aligning the bumps of the semiconductor element with the mounting pads and pressing the semiconductor element against the circuit board to heat it to cure the resin encapsulation a and b.
【００１４】また、上述の硬化工程において併せて封止
樹脂ａ、ｂの真空脱泡を行うか、封止樹脂ａ、ｂに超音
波振動を与えてもよい。Further, vacuum degassing of the sealing resins a and b may be performed at the same time in the above curing step, or ultrasonic vibration may be applied to the sealing resins a and b.
【００１５】[0015]
【実施例】以下本発明の実施例について図面を参照しな
がら詳細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１６】〔実施例１〕図１は本発明の実施例１のフ
リップチップ実装方法を示す回路基板上の実装用パッド
部で切断した断面図である。[Embodiment 1] FIG. 1 is a sectional view showing a flip chip mounting method according to a first embodiment of the present invention, taken along a mounting pad portion on a circuit board.
【００１７】図１（ａ）は未実装の回路基板１である。
回路基板１は実装用パッド３を除く配線がソルダーレジ
スト等の絶縁膜２に覆われていて実装用パッド３がソル
ダーレジスト等の絶縁膜２の溝の底に形成されている。
なお、回路基板１の材質については特に限定されるもの
ではないが、本実施例ではプリント配線板を使用した。
また、絶縁膜２および実装用パッドの厚みに関しても特
に限定されるものではないが、本実施例ではソルダーレ
ジスト２の厚みを４０μｍ、パッド３の厚みを２０μｍ
とした。FIG. 1A shows an unmounted circuit board 1.
The wiring of the circuit board 1 excluding the mounting pads 3 is covered with an insulating film 2 such as a solder resist, and the mounting pads 3 are formed on the bottoms of the grooves of the insulating film 2 such as a solder resist.
The material of the circuit board 1 is not particularly limited, but a printed wiring board is used in this embodiment.
Further, the thicknesses of the insulating film 2 and the mounting pad are not particularly limited, but in the present embodiment, the thickness of the solder resist 2 is 40 μm and the thickness of the pad 3 is 20 μm.
And
【００１８】本実施例では、まず図１（ｂ）に示される
ように、絶縁膜２の溝９に封止樹脂ａ４を供給する。こ
こで供給方法として本実施例ではスクリーン印刷工法を
用いたが、特にこれに限定されるわけではなく、ディス
ペンサーを使用しての供給方法等、公知となっている供
給方法でも行うことができる。また封止樹脂ａ４として
は、溝９への流し込み性が良好のものであれば特に限定
はされないが、本実施例ではエポキシ樹脂系の熱硬化性
樹脂を使用した。本樹脂は、２７０℃で３０ｓｅｃほど
で硬化が完了するものである。In this embodiment, first, as shown in FIG. 1B, the sealing resin a4 is supplied to the groove 9 of the insulating film 2. Although the screen printing method was used as the supply method in this embodiment, the supply method is not particularly limited thereto, and a known supply method such as a supply method using a dispenser may be used. The sealing resin a4 is not particularly limited as long as it has a good pouring property into the groove 9, but an epoxy resin-based thermosetting resin is used in this embodiment. The resin is completely cured at 270 ° C. in about 30 seconds.
【００１９】次に図１（ｃ）に示されるように、図１
（ｂ）の工程後の回路基板１を加熱しながら真空中に放
置し脱泡を行う。ここで、加熱温度は使用する封止樹脂
ａ４の特性により決定されるが、硬化が開始される以前
の温度であって、樹脂の粘度が低下する温度とする。本
実施例では、６０℃とした。また、真空度も樹脂の特性
によって決定されるが、本実施例では５ｍｍＨｇ、１５
分とした（これは評価によって決定されたもので、溝９
中の封止樹脂ａ４に包含されたエアーが完全に排出され
ることを目的としている）。Next, as shown in FIG.
After the step (b), the circuit board 1 is heated and left in a vacuum for defoaming. Here, the heating temperature is determined by the characteristics of the sealing resin a4 to be used, but it is the temperature before the curing is started and is the temperature at which the viscosity of the resin decreases. In this embodiment, the temperature is 60 ° C. The degree of vacuum is also determined by the characteristics of the resin, but in this embodiment, it is 5 mmHg, 15
Minutes (this was determined by evaluation,
The purpose is to completely discharge the air contained in the sealing resin a4).
【００２０】次に図１（ｄ）に示されるように、図１
（ｂ）の工程で供給した封止樹脂ａ４の量では接着力が
不足するためにその不足分として樹脂封止ｂ８を供給す
る。供給方法は図４（ｂ）の工程と同様の方法で行われ
るが、本実施例ではディスペンサーによる供給方法を使
用した。また封止樹脂ｂ８としては、硬化後に半導体素
子６と回路基板１とを接着させる機能を持つものであれ
ば特に限定はされないが、本実施例では封止樹脂ａ４と
は異なるエポキシ樹脂系の即硬化性樹脂を使用した。本
樹脂は、２７０℃で３０ｓｅｃほどで硬化が完了するも
のである。Next, as shown in FIG.
Since the adhesive force is insufficient with the amount of the sealing resin a4 supplied in the step (b), the resin sealing b8 is supplied as the shortage. The supply method is the same as in the step of FIG. 4B, but in this example, the supply method using a dispenser was used. Further, the sealing resin b8 is not particularly limited as long as it has a function of adhering the semiconductor element 6 and the circuit board 1 after curing, but in the present embodiment, an epoxy resin type different from the sealing resin a4 is used. A curable resin was used. The resin is completely cured at 270 ° C. in about 30 seconds.
【００２１】最後に半導体素子６のバンプ電極７と回路
基板１上の実装用パッド３を位置合わせし、封止樹脂ａ
４、ｂ８の真空脱泡を行いながら半導体素子６を加圧・
加熱する。ここで、真空度は５ｍｍＨｇ、加圧量はバン
プ当たり３０ｇ、加熱は半導体素子６側２７０℃、回路
基板１側８０℃、保持時間３０ｓｅｃとした。これらの
条件は使用する封止樹脂ａ４および封止樹脂ｂ８により
変化するものである。Finally, the bump electrodes 7 of the semiconductor element 6 and the mounting pads 3 on the circuit board 1 are aligned, and the sealing resin a
Pressurize the semiconductor element 6 while vacuum defoaming 4, b8
To heat. Here, the degree of vacuum was 5 mmHg, the amount of pressurization was 30 g per bump, the heating was 270 ° C. on the semiconductor element 6 side, the circuit substrate 1 side was 80 ° C., and the holding time was 30 sec. These conditions vary depending on the sealing resin a4 and the sealing resin b8 used.
【００２２】以上の方法により、図２に示すような半導
体素子６の下で封止樹脂ａ４と封止樹脂ｂ８の界面の存
在する本発明の実装基板を得た（界面の状態は多種であ
るが例として図２（ａ）および（ｂ）の２種を示し
た）。By the above method, a mounting board of the present invention having an interface between the sealing resin a4 and the sealing resin b8 under the semiconductor element 6 as shown in FIG. 2 was obtained (the state of the interface is various). Shows two types in FIGS. 2 (a) and 2 (b) as an example).
【００２３】〔実施例２〕上述の実施例１と共に図１を
用いて本発明の実施例２のフリップチップ実装工程を説
明する。[Embodiment 2] A flip chip mounting process according to Embodiment 2 of the present invention will be described with reference to FIG. 1 together with Embodiment 1 described above.
【００２４】本実施例でも未実装の回路基板１は、図１
（ａ）に示すように実装用パッド３がソルダーレジスト
等の絶縁膜２の溝９の底に形成されている。なお、回路
基板１の材質については特に限定されるものではない
が、本実施例ではプリント配線板を使用した。また、絶
縁膜２および実装用パッド３の厚みに関しても特に限定
されるものではないが、本実施例ではソルダーレジスト
２の厚みを４０μｍ、パッド３の厚みを２０μｍとし
た。Also in this embodiment, the unmounted circuit board 1 is as shown in FIG.
As shown in (a), the mounting pad 3 is formed on the bottom of the groove 9 of the insulating film 2 such as a solder resist. The material of the circuit board 1 is not particularly limited, but a printed wiring board is used in this embodiment. Further, the thicknesses of the insulating film 2 and the mounting pad 3 are not particularly limited, but in this embodiment, the solder resist 2 has a thickness of 40 μm and the pad 3 has a thickness of 20 μm.
【００２５】本実施例では、まず図１（ｂ）に示される
ように、絶縁膜２の溝９に封止樹脂ａ４を供給する。こ
こで供給方法として本実施例ではスクリーン印刷工法を
用いたが、特に限定されるわけではなく、ディスペンサ
ーを使用しての供給方法等、公知となっている供給方法
で行われる。また封止樹脂ａ４としては、溝９への流し
込み性が良好のものであれば特に限定されないが、本実
施例ではエポキシ樹脂系の熱硬化性樹脂を使用した。本
樹脂は、２７０℃で３０ｓｅｃほどで硬化が完了するも
のである。In this embodiment, first, as shown in FIG. 1B, the sealing resin a4 is supplied to the groove 9 of the insulating film 2. Although the screen printing method was used as the supply method in this embodiment, the supply method is not particularly limited, and a known supply method such as a supply method using a dispenser may be used. The sealing resin a4 is not particularly limited as long as it has a good pouring property into the groove 9, but an epoxy resin thermosetting resin is used in this embodiment. The resin is completely cured at 270 ° C. in about 30 seconds.
【００２６】次に図１（ｃ）に示されるように、図１
（ｂ）の工程後の回路基板１に超音波による振動を与
え、封止樹脂ａ４に超音波振動を伝えて脱泡を行う。こ
こで、超音波の周波数は２８ｋＨｚとし、振動時間は１
５分とした（これは評価によって決定されたもので、溝
９中の樹脂に包含されたエアーが完全に排出させること
を目的としている）。Next, as shown in FIG.
After the step (b), the circuit board 1 is vibrated by ultrasonic waves, and the ultrasonic vibrations are transmitted to the sealing resin a4 to remove bubbles. Here, the ultrasonic frequency is 28 kHz, and the vibration time is 1
It was set to 5 minutes (this is determined by evaluation and is intended to completely discharge the air contained in the resin in the groove 9).
【００２７】次に図１（ｄ）に示されるように、図１
（ｂ）の工程で供給した樹脂量では接着力が不足するた
めにその不足分として封止樹脂ｂ８を供給する。供給方
法は図１（ｂ）の工程と同様な方法で行われるが、本実
施例ではディスペンサーによる供給方法を使用した。ま
た封止樹脂ｂ８としては、硬化後に半導体素子６と回路
基板１とを接着させる機能を持つものであれば特に限定
はされないが、本実施例では封止樹脂ａ４とは異なるエ
ポキシ樹脂系の即硬化性樹脂を使用した。本樹脂は、２
７０℃で３０ｓｅｃほどで硬化が完了するものである。Next, as shown in FIG.
Since the adhesive amount is insufficient with the amount of resin supplied in the step (b), the sealing resin b8 is supplied as the insufficient amount. The supply method is the same as the step of FIG. 1B, but in this example, the supply method using a dispenser was used. Further, the sealing resin b8 is not particularly limited as long as it has a function of adhering the semiconductor element 6 and the circuit board 1 after curing, but in the present embodiment, an epoxy resin type different from the sealing resin a4 is used. A curable resin was used. This resin is 2
The curing is completed at 70 ° C. for about 30 seconds.
【００２８】最後に半導体素子６のバンプ電極７と回路
基板１上の実装用パッド３を位置合わせし、半導体素子
６に超音波振動を与え、封止樹脂ａ、ｂに超音波振動を
伝えながら加圧・加熱する。ここで、振動周波数は２８
ｋＨｚ、加圧量はバンプ当たり３０ｇ、加熱は素子側２
７０℃、回路基板側８０℃、保持時間３０ｓｅｃとし
た。これらの条件は使用する封止樹脂ａ４および封止樹
脂ｂ８により変化するものである。Finally, the bump electrodes 7 of the semiconductor element 6 and the mounting pads 3 on the circuit board 1 are aligned, ultrasonic vibration is applied to the semiconductor element 6, and ultrasonic vibration is transmitted to the sealing resins a and b. Pressurize and heat. Here, the vibration frequency is 28
kHz, pressurization amount is 30 g per bump, heating is on the element side 2
The temperature was 70 ° C., the circuit board side was 80 ° C., and the holding time was 30 sec. These conditions vary depending on the sealing resin a4 and the sealing resin b8 used.
【００２９】以上の方法により、図２に示すような半導
体素子下で封止樹脂ａと封止樹脂ｂの界面の存在する本
発明の実装基板を得た（界面の状態は多種であるが例と
して図２（ａ）および（ｂ）の２種を示した）。By the above method, a mounting board of the present invention in which an interface between the encapsulating resin a and the encapsulating resin b exists under the semiconductor element as shown in FIG. As shown in FIG. 2 (a) and (b)).
【００３０】なお、上述の実施例１の半導体素子６を加
圧、加熱して封止樹脂ａ４および封止樹脂ｂ８を硬化さ
せる時に真空脱泡の代わりに超音波振動を与えてもよい
し、実施例２で半導体素子６を加圧、加熱して封止樹脂
ａ４および封止樹脂ｂ８を硬化させる時に超音波振動を
与える代わりに真空脱泡を行ってもよい。また、これら
の時に真空脱泡および超音波振動のいずれを行なわなく
ても封止樹脂ａ４の脱泡は行われているので、その分の
半導体素子と回路基板との接合状態の向上が得られる。In addition, ultrasonic vibration may be applied instead of vacuum defoaming when the semiconductor element 6 of the first embodiment described above is pressed and heated to cure the sealing resin a4 and the sealing resin b8. In Example 2, vacuum degassing may be performed instead of applying ultrasonic vibration when the semiconductor element 6 is pressurized and heated to cure the sealing resin a4 and the sealing resin b8. Further, since the sealing resin a4 is degassed without performing vacuum degassing or ultrasonic vibration at these times, the bonding state between the semiconductor element and the circuit board can be improved accordingly. .
【００３１】[0031]
【発明の効果】以上説明したように、本発明のフリップ
チップ実装方法では、回路基板上の絶縁膜の溝に実装パ
ッド部が設けられていても絶縁膜の溝に確実に樹脂を供
給でき、バンプーパッド接合部周辺の封止樹脂にボイド
の発生することがなく確実な接合を得ることができる。
このことから、 温度衝撃試験、プレッシャークッカー試験等の信頼性
評価において確実な向上が確認される。As described above, according to the flip chip mounting method of the present invention, even if the mounting pad portion is provided in the groove of the insulating film on the circuit board, the resin can be surely supplied to the groove of the insulating film. Voids do not occur in the sealing resin around the bump pad bonding portion, and reliable bonding can be obtained.
From this, a reliable improvement is confirmed in reliability evaluations such as a temperature shock test and a pressure cooker test.
【００３２】実装直後の初期歩留まりが向上する。The initial yield immediately after mounting is improved.
【００３３】という効果がある。There is an effect.
【図１】本発明の実施例１および２のフリップチップ実
装方法を工程順に示す断面図である。FIG. 1 is a cross-sectional view showing a flip-chip mounting method according to first and second embodiments of the present invention in the order of steps.
【図２】図１に示す実施例で実装された半導体素子の断
面図である。FIG. 2 is a sectional view of a semiconductor device mounted in the embodiment shown in FIG.
【図３】従来のフリップチップ実装方法による半導体素
子の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device manufactured by a conventional flip chip mounting method.
１ 回路基板 ２ 絶縁膜 ３ 実装用パッド ４ 封止樹脂ａ ５ 気泡 ６ 半導体素子 ７ バンプ ８ 封止樹脂ｂ ９ 溝 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Insulating film 3 Mounting pad 4 Sealing resin a 5 Bubbles 6 Semiconductor element 7 Bump 8 Sealing resin b 9 Groove
Claims (4)
用パッドが配設された溝に封止樹脂ａを供給する第１の
供給工程と、この第１の供給工程の次に前記封止樹脂ａ
を真空脱泡する脱泡工程と、この脱泡工程の次に前記回
路基板上の半導体素子の実装部中央に封止樹脂ｂを供給
する第２の供給工程と、前記半導体素子のバンプと前記
実装用パッドとを位置合わせして前記半導体素子を前記
回路基板に押し付けて加熱し前記封止樹脂ａ、ｂを硬化
させる硬化工程とを含むことを特徴とするフリップチッ
プ実装方法。1. A first supply step of supplying a sealing resin a to a groove formed in an insulating film covering a circuit board and having a mounting pad on the bottom thereof, and the first supply step is followed by the first supply step. Sealing resin a
A defoaming step of vacuum defoaming, a second supplying step of supplying a sealing resin b to the center of the mounting portion of the semiconductor element on the circuit board, and a bump of the semiconductor element A flip chip mounting method, which includes a curing step of aligning a mounting pad and pressing the semiconductor element against the circuit board to heat the sealing resin a and b to cure the sealing resin a and b.
用パッドが配設された溝に封止樹脂ａを供給する第１の
供給工程と、この第１の供給工程の次に前記封止樹脂ａ
に超音波振動を与える脱泡工程と、この脱泡工程の次に
前記回路基板上の半導体素子の実装部中央に封止樹脂ｂ
を供給する第２の供給工程と、前記半導体素子のバンプ
と前記実装用パッドとを位置合わせして前記半導体素子
を前記回路基板に押し付けて加熱し前記樹脂封止ａ、ｂ
を硬化させる硬化工程とを含むことを特徴とするフリッ
プチップ実装方法。2. A first supplying step of supplying a sealing resin a to a groove formed in an insulating film covering a circuit board and having a mounting pad at the bottom, and the first supplying step and the following step. Sealing resin a
Defoaming step in which ultrasonic vibration is applied to the substrate, and next to this defoaming step, the sealing resin b is provided at the center of the mounting portion of the semiconductor element on the circuit board.
And a second supplying step for supplying the semiconductor element, the bump of the semiconductor element and the mounting pad are aligned, the semiconductor element is pressed against the circuit board and heated, and the resin sealing a, b is performed.
A flip chip mounting method, comprising:
の真空脱泡を行うことを特徴とする請求項１または２に
記載のフリップチップ実装方法。3. A resin encapsulation a, b in combination with a curing step.
3. The flip chip mounting method according to claim 1, wherein the vacuum degassing is performed.
ｂに超音波振動を与えることを特徴とする請求項１また
は２に記載のフリップチップ実装方法。4. A resin encapsulating resin a.
The flip chip mounting method according to claim 1, wherein ultrasonic vibration is applied to b.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29285194A JP2555994B2 (en) | 1994-11-28 | 1994-11-28 | Flip chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29285194A JP2555994B2 (en) | 1994-11-28 | 1994-11-28 | Flip chip mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08153752A true JPH08153752A (en) | 1996-06-11 |
| JP2555994B2 JP2555994B2 (en) | 1996-11-20 |
Family
ID=17787196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29285194A Expired - Lifetime JP2555994B2 (en) | 1994-11-28 | 1994-11-28 | Flip chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2555994B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6212768B1 (en) | 1998-05-15 | 2001-04-10 | Nec Corporation | Flip chip mounting method and apparatus therefor |
| SG108931A1 (en) * | 2002-09-02 | 2005-02-28 | Murata Manufacturing Co | Mounting board and electronic device using the same |
| KR100766503B1 (en) * | 2006-09-20 | 2007-10-15 | 삼성전자주식회사 | Semiconductor device package |
| JP2008004608A (en) * | 2006-06-20 | 2008-01-10 | Matsushita Electric Ind Co Ltd | Method for packaging electronic component |
| US8587019B2 (en) | 2011-10-11 | 2013-11-19 | Ledengin, Inc. | Grooved plate for improved solder bonding |
| JP2020188042A (en) * | 2019-05-10 | 2020-11-19 | 三菱電機株式会社 | Semiconductor device, power conversion device, and method of manufacturing semiconductor device |
-
1994
- 1994-11-28 JP JP29285194A patent/JP2555994B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6212768B1 (en) | 1998-05-15 | 2001-04-10 | Nec Corporation | Flip chip mounting method and apparatus therefor |
| SG108931A1 (en) * | 2002-09-02 | 2005-02-28 | Murata Manufacturing Co | Mounting board and electronic device using the same |
| US7005585B2 (en) | 2002-09-02 | 2006-02-28 | Murata Manufacturing Co., Ltd. | Mounting board and electronic device using same |
| JP2008004608A (en) * | 2006-06-20 | 2008-01-10 | Matsushita Electric Ind Co Ltd | Method for packaging electronic component |
| KR100766503B1 (en) * | 2006-09-20 | 2007-10-15 | 삼성전자주식회사 | Semiconductor device package |
| US8587019B2 (en) | 2011-10-11 | 2013-11-19 | Ledengin, Inc. | Grooved plate for improved solder bonding |
| JP2020188042A (en) * | 2019-05-10 | 2020-11-19 | 三菱電機株式会社 | Semiconductor device, power conversion device, and method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2555994B2 (en) | 1996-11-20 |
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