ITRM20030365A0 - Ricostruzione di stimolo di tester algoritmico non-deterministico usato come ingresso per un dispositivo sotto collaudo. - Google Patents

Ricostruzione di stimolo di tester algoritmico non-deterministico usato come ingresso per un dispositivo sotto collaudo.

Info

Publication number
ITRM20030365A0
ITRM20030365A0 IT2003RM000365A ITRM20030365A ITRM20030365A0 IT RM20030365 A0 ITRM20030365 A0 IT RM20030365A0 IT 2003RM000365 A IT2003RM000365 A IT 2003RM000365A IT RM20030365 A ITRM20030365 A IT RM20030365A IT RM20030365 A0 ITRM20030365 A0 IT RM20030365A0
Authority
IT
Italy
Prior art keywords
reconstruction
input
device under
under testing
stimulus used
Prior art date
Application number
IT2003RM000365A
Other languages
English (en)
Inventor
Stephen Dennis Jordan
Hsiu-Huan Shen
Alan S Krech Jr
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of ITRM20030365A0 publication Critical patent/ITRM20030365A0/it
Publication of ITRM20030365A1 publication Critical patent/ITRM20030365A1/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/25—Testing of logic operation, e.g. by logic analysers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
IT000365A 2002-07-26 2003-07-25 Ricostruzione di stimolo di tester algoritmico ITRM20030365A1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/206,264 US7181660B2 (en) 2002-07-26 2002-07-26 Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test

Publications (2)

Publication Number Publication Date
ITRM20030365A0 true ITRM20030365A0 (it) 2003-07-25
ITRM20030365A1 ITRM20030365A1 (it) 2004-01-27

Family

ID=29780257

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000365A ITRM20030365A1 (it) 2002-07-26 2003-07-25 Ricostruzione di stimolo di tester algoritmico

Country Status (3)

Country Link
US (1) US7181660B2 (it)
JP (1) JP4206431B2 (it)
IT (1) ITRM20030365A1 (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005033906A2 (en) * 2003-09-30 2005-04-14 Mentor Graphics Corporation System verification using one or more automata
US20090112548A1 (en) * 2007-10-30 2009-04-30 Conner George W A method for testing in a reconfigurable tester
US20090113245A1 (en) * 2007-10-30 2009-04-30 Teradyne, Inc. Protocol aware digital channel apparatus
US20090119542A1 (en) * 2007-11-05 2009-05-07 Advantest Corporation System, method, and program product for simulating test equipment
US8195419B2 (en) * 2009-03-13 2012-06-05 Teradyne, Inc. General purpose protocol engine
MY166393A (en) * 2010-05-05 2018-06-25 Teradyne Inc System for concurrent test of semiconductor devices
US10419890B2 (en) * 2012-06-15 2019-09-17 Qualcomm Incorporated Client access to mobile location services
US10254125B2 (en) * 2016-11-14 2019-04-09 International Business Machines Corporation Driving assistant system
TWI661208B (zh) * 2017-10-11 2019-06-01 致茂電子股份有限公司 測試裝置及其測試電路板
US11287630B2 (en) * 2019-09-03 2022-03-29 International Business Machines Corporation Imaging integrated circuits using a single-point single-photon detector and a scanning system and calculating of a per-pixel value
CN113450865B (zh) * 2020-03-26 2022-05-20 长鑫存储技术有限公司 存储器测试系统及其测试方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680518A (en) * 1994-08-26 1997-10-21 Hangartner; Ricky D. Probabilistic computing methods and apparatus
US5748642A (en) * 1995-09-25 1998-05-05 Credence Systems Corporation Parallel processing integrated circuit tester
DE69940061D1 (de) * 1999-09-30 2009-01-22 St Microelectronics Srl Speicherprüfverfahren und nicht-fluchtiger Speicher mit niedriger Fehlerverdeckungswahrscheinlichkeit
US6681351B1 (en) * 1999-10-12 2004-01-20 Teradyne, Inc. Easy to program automatic test equipment
US20040006447A1 (en) * 2000-06-22 2004-01-08 Jacky Gorin Methods and apparatus for test process enhancement

Also Published As

Publication number Publication date
US20040019839A1 (en) 2004-01-29
JP2004061509A (ja) 2004-02-26
ITRM20030365A1 (it) 2004-01-27
US7181660B2 (en) 2007-02-20
JP4206431B2 (ja) 2009-01-14

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