DE69940061D1 - Speicherprüfverfahren und nicht-fluchtiger Speicher mit niedriger Fehlerverdeckungswahrscheinlichkeit - Google Patents

Speicherprüfverfahren und nicht-fluchtiger Speicher mit niedriger Fehlerverdeckungswahrscheinlichkeit

Info

Publication number
DE69940061D1
DE69940061D1 DE69940061T DE69940061T DE69940061D1 DE 69940061 D1 DE69940061 D1 DE 69940061D1 DE 69940061 T DE69940061 T DE 69940061T DE 69940061 T DE69940061 T DE 69940061T DE 69940061 D1 DE69940061 D1 DE 69940061D1
Authority
DE
Germany
Prior art keywords
memory
signature code
read
data
error concealment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69940061T
Other languages
English (en)
Inventor
Promod Kumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69940061D1 publication Critical patent/DE69940061D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69940061T 1999-09-30 1999-09-30 Speicherprüfverfahren und nicht-fluchtiger Speicher mit niedriger Fehlerverdeckungswahrscheinlichkeit Expired - Lifetime DE69940061D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP99830617A EP1089293B1 (de) 1999-09-30 1999-09-30 Speicherprüfverfahren und nicht-fluchtiger Speicher mit niedriger Fehlerverdeckungswahrscheinlichkeit

Publications (1)

Publication Number Publication Date
DE69940061D1 true DE69940061D1 (de) 2009-01-22

Family

ID=8243605

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69940061T Expired - Lifetime DE69940061D1 (de) 1999-09-30 1999-09-30 Speicherprüfverfahren und nicht-fluchtiger Speicher mit niedriger Fehlerverdeckungswahrscheinlichkeit

Country Status (3)

Country Link
US (1) US6282134B1 (de)
EP (1) EP1089293B1 (de)
DE (1) DE69940061D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6389525B1 (en) * 1999-01-08 2002-05-14 Teradyne, Inc. Pattern generator for a packet-based memory tester
US6834364B2 (en) * 2001-04-19 2004-12-21 Agilent Technologies, Inc. Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences
US7181660B2 (en) * 2002-07-26 2007-02-20 Verigy Pte. Ltd. Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test
US6738294B2 (en) * 2002-09-30 2004-05-18 Agere Systems Inc. Electronic fingerprinting of semiconductor integrated circuits
US20040193984A1 (en) * 2003-03-28 2004-09-30 Stmicroelectronics Inc. Signature Cell
US7376887B2 (en) * 2003-12-22 2008-05-20 International Business Machines Corporation Method for fast ECC memory testing by software including ECC check byte
US7117415B2 (en) * 2004-01-15 2006-10-03 International Business Machines Corporation Automated BIST test pattern sequence generator software system and method
US7584386B2 (en) * 2004-04-21 2009-09-01 Stmicroelectronics Sa Microprocessor comprising error detection means protected against an attack by error injection
DE102004043050B4 (de) * 2004-09-06 2006-08-17 Infineon Technologies Ag Verfahren, Halbleitervorrichtung und Testsystem zur Loop-back-Vermessung des Interface-Timings von Halbleitervorrichtungen
US7707467B2 (en) * 2007-02-23 2010-04-27 Micron Technology, Inc. Input/output compression and pin reduction in an integrated circuit
TWI552159B (zh) * 2015-02-24 2016-10-01 晶豪科技股份有限公司 產生位址的方法
US9601193B1 (en) * 2015-09-14 2017-03-21 Intel Corporation Cross point memory control

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2511028B2 (ja) * 1987-04-24 1996-06-26 日本電信電話株式会社 メモリテスト方法
JP2833574B2 (ja) * 1996-03-28 1998-12-09 日本電気株式会社 不揮発性半導体記憶装置
JP2000011700A (ja) * 1998-06-25 2000-01-14 Nec Ic Microcomput Syst Ltd Ｒｏｍのテスト方法及びｒｏｍのテスト回路

Also Published As

Publication number Publication date
EP1089293A1 (de) 2001-04-04
US6282134B1 (en) 2001-08-28
EP1089293B1 (de) 2008-12-10

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Legal Events

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