ITMI913187A1 - Struttura circuitale a registri distribuiti con lettura e scrittura autotemporizzate - Google Patents

Struttura circuitale a registri distribuiti con lettura e scrittura autotemporizzate

Info

Publication number
ITMI913187A1
ITMI913187A1 IT003187A ITMI913187A ITMI913187A1 IT MI913187 A1 ITMI913187 A1 IT MI913187A1 IT 003187 A IT003187 A IT 003187A IT MI913187 A ITMI913187 A IT MI913187A IT MI913187 A1 ITMI913187 A1 IT MI913187A1
Authority
IT
Italy
Prior art keywords
autotemporized
writing
reading
circuit structure
registers distributed
Prior art date
Application number
IT003187A
Other languages
English (en)
Inventor
Giorgio Betti
David Moloney
Fabrizio Sacchi
Gianfranco Vai
Maurizio Zuffada
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to ITMI913187A priority Critical patent/IT1252017B/it
Publication of ITMI913187A0 publication Critical patent/ITMI913187A0/it
Priority to EP19920203580 priority patent/EP0544370A3/en
Priority to US07/979,960 priority patent/US5408436A/en
Priority to JP4315028A priority patent/JPH05241782A/ja
Publication of ITMI913187A1 publication Critical patent/ITMI913187A1/it
Application granted granted Critical
Publication of IT1252017B publication Critical patent/IT1252017B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)
ITMI913187A 1991-11-28 1991-11-28 Struttura circuitale a registri distribuiti con lettura e scrittura autotemporizzate IT1252017B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
ITMI913187A IT1252017B (it) 1991-11-28 1991-11-28 Struttura circuitale a registri distribuiti con lettura e scrittura autotemporizzate
EP19920203580 EP0544370A3 (en) 1991-11-28 1992-11-20 Circuit structure having distributed registers with self-timed reading and writing operations
US07/979,960 US5408436A (en) 1991-11-28 1992-11-23 Circuit structure having distributed registers with self-timed reading and writing operations
JP4315028A JPH05241782A (ja) 1991-11-28 1992-11-25 自己時間調整の下で読出し及び書込み動作をする分散形レジスタを持つ回路構成

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI913187A IT1252017B (it) 1991-11-28 1991-11-28 Struttura circuitale a registri distribuiti con lettura e scrittura autotemporizzate

Publications (3)

Publication Number Publication Date
ITMI913187A0 ITMI913187A0 (it) 1991-11-28
ITMI913187A1 true ITMI913187A1 (it) 1993-05-28
IT1252017B IT1252017B (it) 1995-05-27

Family

ID=11361211

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI913187A IT1252017B (it) 1991-11-28 1991-11-28 Struttura circuitale a registri distribuiti con lettura e scrittura autotemporizzate

Country Status (4)

Country Link
US (1) US5408436A (it)
EP (1) EP0544370A3 (it)
JP (1) JPH05241782A (it)
IT (1) IT1252017B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0135231B1 (ko) * 1994-08-23 1998-04-22 김주용 고속 테스트 기능을 갖는 메모리 소자
US5633605A (en) * 1995-05-24 1997-05-27 International Business Machines Corporation Dynamic bus with singular central precharge
KR100256902B1 (ko) * 1997-06-24 2000-05-15 김영환 반도체 메모리 소자의 제어회로

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186827A (ja) * 1982-04-23 1983-10-31 Oki Electric Ind Co Ltd マイクロプロセツサ
JPS60179993A (ja) * 1984-02-27 1985-09-13 Toshiba Corp ランダムアクセスメモリ
EP0206743A3 (en) * 1985-06-20 1990-04-25 Texas Instruments Incorporated Zero fall-through time asynchronous fifo buffer with nonambiguous empty/full resolution
US5018111A (en) * 1988-12-27 1991-05-21 Intel Corporation Timing circuit for memory employing reset function
JPH0373495A (ja) * 1989-02-15 1991-03-28 Ricoh Co Ltd 半導体メモリ装置
US5084839A (en) * 1990-02-05 1992-01-28 Harris Corporation Variable length shift register
KR930006622B1 (ko) * 1990-09-04 1993-07-21 삼성전자 주식회사 반도체 메모리장치

Also Published As

Publication number Publication date
JPH05241782A (ja) 1993-09-21
EP0544370A2 (en) 1993-06-02
IT1252017B (it) 1995-05-27
ITMI913187A0 (it) 1991-11-28
EP0544370A3 (en) 1993-11-10
US5408436A (en) 1995-04-18

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129