ITMI20042535A1 - Dispositivo di memoria - Google Patents

Dispositivo di memoria

Info

Publication number
ITMI20042535A1
ITMI20042535A1 IT002535A ITMI20042535A ITMI20042535A1 IT MI20042535 A1 ITMI20042535 A1 IT MI20042535A1 IT 002535 A IT002535 A IT 002535A IT MI20042535 A ITMI20042535 A IT MI20042535A IT MI20042535 A1 ITMI20042535 A1 IT MI20042535A1
Authority
IT
Italy
Prior art keywords
memory device
memory
Prior art date
Application number
IT002535A
Other languages
English (en)
Inventor
Gianluca Blasi
Barbara Vese
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT002535A priority Critical patent/ITMI20042535A1/it
Publication of ITMI20042535A1 publication Critical patent/ITMI20042535A1/it
Priority to EP05425899A priority patent/EP1677309A3/en
Priority to US11/319,799 priority patent/US7339845B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
IT002535A 2004-12-28 2004-12-28 Dispositivo di memoria ITMI20042535A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT002535A ITMI20042535A1 (it) 2004-12-28 2004-12-28 Dispositivo di memoria
EP05425899A EP1677309A3 (en) 2004-12-28 2005-12-20 Memory device
US11/319,799 US7339845B2 (en) 2004-12-28 2005-12-27 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT002535A ITMI20042535A1 (it) 2004-12-28 2004-12-28 Dispositivo di memoria

Publications (1)

Publication Number Publication Date
ITMI20042535A1 true ITMI20042535A1 (it) 2005-03-28

Family

ID=36081316

Family Applications (1)

Application Number Title Priority Date Filing Date
IT002535A ITMI20042535A1 (it) 2004-12-28 2004-12-28 Dispositivo di memoria

Country Status (3)

Country Link
US (1) US7339845B2 (it)
EP (1) EP1677309A3 (it)
IT (1) ITMI20042535A1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7688648B2 (en) * 2008-09-02 2010-03-30 Juhan Kim High speed flash memory
US20140126273A1 (en) * 2012-11-02 2014-05-08 International Business Machines Corporation Power management sram global bit line precharge circuit
US10289186B1 (en) * 2013-10-31 2019-05-14 Maxim Integrated Products, Inc. Systems and methods to improve energy efficiency using adaptive mode switching

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3365595B2 (ja) * 1994-12-21 2003-01-14 シャープ株式会社 半導体記憶装置及びその駆動方法
US6490225B1 (en) * 2001-12-04 2002-12-03 Motorola, Inc. Memory having a synchronous controller and asynchronous array and method thereof
US6501695B1 (en) * 2002-01-11 2002-12-31 Lsi Logic Corporation Technique for the reduction of memory access time variation
JP4408610B2 (ja) * 2002-08-09 2010-02-03 株式会社ルネサステクノロジ スタティック型半導体記憶装置

Also Published As

Publication number Publication date
EP1677309A3 (en) 2006-09-06
EP1677309A2 (en) 2006-07-05
US20060171222A1 (en) 2006-08-03
US7339845B2 (en) 2008-03-04

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