IT9022437A0 - Circuito di generazione di un clock di scansione in un dispositivo di analisi operativa di tipo seriale per circuito integrato - Google Patents
Circuito di generazione di un clock di scansione in un dispositivo di analisi operativa di tipo seriale per circuito integratoInfo
- Publication number
- IT9022437A0 IT9022437A0 IT22437A IT2243790A IT9022437A0 IT 9022437 A0 IT9022437 A0 IT 9022437A0 IT 22437 A IT22437 A IT 22437A IT 2243790 A IT2243790 A IT 2243790A IT 9022437 A0 IT9022437 A0 IT 9022437A0
- Authority
- IT
- Italy
- Prior art keywords
- analysis device
- clock generation
- scan clock
- serial type
- integrated circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT02243790A IT1244205B (it) | 1990-12-19 | 1990-12-19 | Circuito di generazione di un clock di scansione in un dispositivo di analisi operativa di tipo seriale per circuito integrato |
DE69125256T DE69125256T2 (de) | 1990-12-19 | 1991-12-11 | Schaltung zur Erzeugung des Abtasttaktes in einer Vorrichtung zur seriellen Untersuchung der Arbeitsweise einer integrierten Schaltung |
EP91203231A EP0491425B1 (en) | 1990-12-19 | 1991-12-11 | Circuit for the generation of a scanning clock in an operational analysis device of the serial type for an integrated circuit |
US07/812,135 US5220217A (en) | 1990-12-19 | 1991-12-18 | Circuit for the generation of a scanning clock in an operational anaylsis device of the serial type for an integrated circuit |
KR1019910023404A KR920013908A (ko) | 1990-12-19 | 1991-12-19 | 집적회로용 순차형 조작분석 장치에서 주사클럭 발생을 위한 회로 |
JP33699391A JP3188297B2 (ja) | 1990-12-19 | 1991-12-19 | 集積回路のための直列型の動作分析装置に走査クロックを発生させるための回路 |
US08/492,462 USRE36123E (en) | 1990-12-19 | 1995-06-15 | Circuit for the generation of a scanning clock in an operational analysis device of the serial type for an integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT02243790A IT1244205B (it) | 1990-12-19 | 1990-12-19 | Circuito di generazione di un clock di scansione in un dispositivo di analisi operativa di tipo seriale per circuito integrato |
Publications (3)
Publication Number | Publication Date |
---|---|
IT9022437A0 true IT9022437A0 (it) | 1990-12-19 |
IT9022437A1 IT9022437A1 (it) | 1992-06-19 |
IT1244205B IT1244205B (it) | 1994-07-08 |
Family
ID=11196301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT02243790A IT1244205B (it) | 1990-12-19 | 1990-12-19 | Circuito di generazione di un clock di scansione in un dispositivo di analisi operativa di tipo seriale per circuito integrato |
Country Status (6)
Country | Link |
---|---|
US (2) | US5220217A (it) |
EP (1) | EP0491425B1 (it) |
JP (1) | JP3188297B2 (it) |
KR (1) | KR920013908A (it) |
DE (1) | DE69125256T2 (it) |
IT (1) | IT1244205B (it) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE36292E (en) * | 1990-10-22 | 1999-09-07 | Stmicroelectronics, Inc. | Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit |
US5336939A (en) * | 1992-05-08 | 1994-08-09 | Cyrix Corporation | Stable internal clock generation for an integrated circuit |
US5341048A (en) * | 1992-11-25 | 1994-08-23 | Altera Corporation | Clock invert and select circuit |
JPH06242188A (ja) * | 1993-02-16 | 1994-09-02 | Mitsubishi Electric Corp | 半導体集積回路及びそのテスト方法 |
DE4321315C1 (de) * | 1993-06-26 | 1995-01-05 | Itt Ind Gmbh Deutsche | Takterzeugungsschaltung für taktgesteuerte Logikschaltungen |
US5491441A (en) * | 1994-06-30 | 1996-02-13 | International Business Machines Corporation | Method and apparatus for generating a clock signal from a continuous oscillator signal including a translator circuit |
TW418329B (en) * | 1994-08-24 | 2001-01-11 | Ibm | Integrated circuit clocking technique and circuit therefor |
US5850150A (en) * | 1996-05-01 | 1998-12-15 | Sun Microsystems, Inc. | Final stage clock buffer in a clock distribution network |
JPH1091270A (ja) * | 1996-09-13 | 1998-04-10 | Sanyo Electric Co Ltd | クロック制御方法およびその方法を用いた集積回路素子 |
KR100272672B1 (ko) * | 1997-12-31 | 2000-11-15 | 윤종용 | 다이나믹 씨모오스 회로 |
US7992062B2 (en) * | 2006-06-22 | 2011-08-02 | Qualcomm Incorporated | Logic device and method supporting scan test |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4245349A (en) * | 1977-12-29 | 1981-01-13 | Nippon Gakki Seizo Kabushiki Kaisha | Automatic frequency scanning radio receiver |
US4308472A (en) * | 1979-12-03 | 1981-12-29 | Gte Automatic Electric Labs Inc. | Clock check circuit |
DE3106183A1 (de) * | 1981-02-19 | 1982-09-02 | Siemens AG, 1000 Berlin und 8000 München | Verfahren und anordnung zur fehlerfreien synchronisation asynchroner impulse |
US4441182A (en) * | 1981-05-15 | 1984-04-03 | Rockwell International Corporation | Repetitious logic state signal generation apparatus |
US4413077A (en) * | 1981-06-22 | 1983-11-01 | Borg-Warner Chemicals, Inc. | Oligomeric aromatic polyphosphites |
US4493077A (en) * | 1982-09-09 | 1985-01-08 | At&T Laboratories | Scan testable integrated circuit |
JPS59151537A (ja) * | 1983-01-29 | 1984-08-30 | Toshiba Corp | 相補mos形回路 |
US4627085A (en) * | 1984-06-29 | 1986-12-02 | Applied Micro Circuits Corporation | Flip-flop control circuit |
US4710933A (en) * | 1985-10-23 | 1987-12-01 | Texas Instruments Incorporated | Parallel/serial scan system for testing logic circuits |
US4649539A (en) * | 1985-11-04 | 1987-03-10 | Honeywell Information Systems Inc. | Apparatus providing improved diagnosability |
US4701920A (en) * | 1985-11-08 | 1987-10-20 | Eta Systems, Inc. | Built-in self-test system for VLSI circuit chips |
GB2188504B (en) * | 1986-03-27 | 1989-11-22 | Intel Corp | Cmos single clock logic arrangement |
JPS62272722A (ja) * | 1986-05-21 | 1987-11-26 | Clarion Co Ltd | Ttl論理レベルcmos入力バツフア |
US4922138A (en) * | 1987-05-25 | 1990-05-01 | Canon Kabushiki Kaisha | Scan circuit using a plural bootstrap effect for forming scan pulses |
GB8728359D0 (en) * | 1987-12-04 | 1988-01-13 | Brown Boveri Plc | Improvements in metering apparatus |
IT1246301B (it) * | 1990-10-22 | 1994-11-17 | St Microelectronics Srl | Dispositivo di analisi operativa di tipo scan path a singolo clock di scansione e singola fase di uscita per circuito integrato. |
-
1990
- 1990-12-19 IT IT02243790A patent/IT1244205B/it active IP Right Grant
-
1991
- 1991-12-11 DE DE69125256T patent/DE69125256T2/de not_active Expired - Fee Related
- 1991-12-11 EP EP91203231A patent/EP0491425B1/en not_active Expired - Lifetime
- 1991-12-18 US US07/812,135 patent/US5220217A/en not_active Ceased
- 1991-12-19 JP JP33699391A patent/JP3188297B2/ja not_active Expired - Fee Related
- 1991-12-19 KR KR1019910023404A patent/KR920013908A/ko not_active Application Discontinuation
-
1995
- 1995-06-15 US US08/492,462 patent/USRE36123E/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0491425B1 (en) | 1997-03-19 |
IT1244205B (it) | 1994-07-08 |
JPH04335172A (ja) | 1992-11-24 |
USRE36123E (en) | 1999-03-02 |
US5220217A (en) | 1993-06-15 |
EP0491425A3 (en) | 1993-11-10 |
DE69125256D1 (de) | 1997-04-24 |
IT9022437A1 (it) | 1992-06-19 |
DE69125256T2 (de) | 1997-07-17 |
EP0491425A2 (en) | 1992-06-24 |
JP3188297B2 (ja) | 2001-07-16 |
KR920013908A (ko) | 1992-07-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19961227 |