IT1320666B1 - Circuito di comando di un regolatore di tensione variabile di unamemoria non volatile con decodifica gerarchica di riga. - Google Patents

Circuito di comando di un regolatore di tensione variabile di unamemoria non volatile con decodifica gerarchica di riga.

Info

Publication number
IT1320666B1
IT1320666B1 IT2000TO000892A ITTO20000892A IT1320666B1 IT 1320666 B1 IT1320666 B1 IT 1320666B1 IT 2000TO000892 A IT2000TO000892 A IT 2000TO000892A IT TO20000892 A ITTO20000892 A IT TO20000892A IT 1320666 B1 IT1320666 B1 IT 1320666B1
Authority
IT
Italy
Prior art keywords
control circuit
volatile memory
voltage regulator
variable voltage
line decoding
Prior art date
Application number
IT2000TO000892A
Other languages
English (en)
Inventor
Andrea Sacco
Osama Khouri
Rino Micheloni
Guido Torelli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2000TO000892A priority Critical patent/IT1320666B1/it
Publication of ITTO20000892A0 publication Critical patent/ITTO20000892A0/it
Priority to US09/960,851 priority patent/US6504758B2/en
Publication of ITTO20000892A1 publication Critical patent/ITTO20000892A1/it
Application granted granted Critical
Publication of IT1320666B1 publication Critical patent/IT1320666B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT2000TO000892A 2000-09-22 2000-09-22 Circuito di comando di un regolatore di tensione variabile di unamemoria non volatile con decodifica gerarchica di riga. IT1320666B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2000TO000892A IT1320666B1 (it) 2000-09-22 2000-09-22 Circuito di comando di un regolatore di tensione variabile di unamemoria non volatile con decodifica gerarchica di riga.
US09/960,851 US6504758B2 (en) 2000-09-22 2001-09-21 Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2000TO000892A IT1320666B1 (it) 2000-09-22 2000-09-22 Circuito di comando di un regolatore di tensione variabile di unamemoria non volatile con decodifica gerarchica di riga.

Publications (3)

Publication Number Publication Date
ITTO20000892A0 ITTO20000892A0 (it) 2000-09-22
ITTO20000892A1 ITTO20000892A1 (it) 2002-03-22
IT1320666B1 true IT1320666B1 (it) 2003-12-10

Family

ID=11458061

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2000TO000892A IT1320666B1 (it) 2000-09-22 2000-09-22 Circuito di comando di un regolatore di tensione variabile di unamemoria non volatile con decodifica gerarchica di riga.

Country Status (2)

Country Link
US (1) US6504758B2 (it)
IT (1) IT1320666B1 (it)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4149637B2 (ja) * 2000-05-25 2008-09-10 株式会社東芝 半導体装置
JP4796238B2 (ja) * 2001-04-27 2011-10-19 Ｏｋｉセミコンダクタ株式会社 ワード線駆動回路
EP1434233B1 (en) * 2001-12-28 2018-01-24 Micron Technology, Inc. power supply circuit structure for a row decoder of a multilevel non-volatile memory device
US6815998B1 (en) * 2002-10-22 2004-11-09 Xilinx, Inc. Adjustable-ratio global read-back voltage generator
ITMI20042241A1 (it) * 2004-11-19 2005-02-19 St Microelectronics Srl Metodo di configurazione di un regolatore di tensione
KR100610020B1 (ko) 2005-01-13 2006-08-08 삼성전자주식회사 반도체 메모리 장치에서의 셀 파워 스위칭 회로와 그에따른 셀 파워 전압 인가방법
JP5123478B2 (ja) 2005-10-24 2013-01-23 ユニ・チャーム株式会社 吸収性物品
DE102008027392B4 (de) * 2008-06-09 2019-03-21 Atmel Corp. Schaltung und Verfahren zum Betrieb einer Schaltung
KR20140009712A (ko) * 2012-07-12 2014-01-23 삼성전자주식회사 전압 레귤레이터, 전압 레귤레이팅 시스템, 메모리 칩, 및 메모리 장치
WO2015031055A1 (en) * 2013-08-29 2015-03-05 International Business Machines Corporation Passgate strength calibration techniques for voltage regulators
US9013927B1 (en) 2013-10-10 2015-04-21 Freescale Semiconductor, Inc. Sector-based regulation of program voltages for non-volatile memory (NVM) systems
US9269442B2 (en) 2014-02-20 2016-02-23 Freescale Semiconductor, Inc. Digital control for regulation of program voltages for non-volatile memory (NVM) systems
US9832048B2 (en) * 2015-08-24 2017-11-28 Xilinx, Inc. Transmitter circuit for and methods of generating a modulated signal in a transmitter
JP2018045750A (ja) * 2016-09-16 2018-03-22 東芝メモリ株式会社 半導体記憶装置
US9792979B1 (en) * 2016-11-30 2017-10-17 Apple Inc. Process, voltage, and temperature tracking SRAM retention voltage regulator
US10608630B1 (en) * 2018-06-26 2020-03-31 Xilinx, Inc. Method of increased supply rejection on single-ended complementary metal-oxide-semiconductor (CMOS) switches

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3370563B2 (ja) * 1997-07-09 2003-01-27 シャープ株式会社 不揮発性半導体記憶装置の駆動方法
US5991198A (en) * 1998-04-02 1999-11-23 Nexflash Technologies, Inc. Local row decoder and associated control logic for fowler-nordheim tunneling based flash memory
DE69937559T2 (de) * 1999-09-10 2008-10-23 Stmicroelectronics S.R.L., Agrate Brianza Nicht-flüchtige Speicher mit Erkennung von Kurzschlüssen zwischen Wortleitungen

Also Published As

Publication number Publication date
ITTO20000892A0 (it) 2000-09-22
US20020097627A1 (en) 2002-07-25
US6504758B2 (en) 2003-01-07
ITTO20000892A1 (it) 2002-03-22

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