IT1248750B - Metodo per memorizzare dati in un test di un dispositivo di memoria e circuito per testare un dispositivo di memoria - Google Patents
Metodo per memorizzare dati in un test di un dispositivo di memoria e circuito per testare un dispositivo di memoriaInfo
- Publication number
- IT1248750B IT1248750B IT02056690A IT2056690A IT1248750B IT 1248750 B IT1248750 B IT 1248750B IT 02056690 A IT02056690 A IT 02056690A IT 2056690 A IT2056690 A IT 2056690A IT 1248750 B IT1248750 B IT 1248750B
- Authority
- IT
- Italy
- Prior art keywords
- memory device
- testing
- test
- circuit
- storing data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890008002A KR920001080B1 (ko) | 1989-06-10 | 1989-06-10 | 메모리소자의 데이타 기록 방법 및 테스트 회로 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| IT9020566A0 IT9020566A0 (ko) | 1990-06-07 |
| IT9020566A1 IT9020566A1 (it) | 1991-12-07 |
| IT1248750B true IT1248750B (it) | 1995-01-27 |
Family
ID=19286971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT02056690A IT1248750B (it) | 1989-06-10 | 1990-06-07 | Metodo per memorizzare dati in un test di un dispositivo di memoria e circuito per testare un dispositivo di memoria |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JP3101953B2 (ko) |
| KR (1) | KR920001080B1 (ko) |
| CN (1) | CN1019243B (ko) |
| DE (1) | DE4003132A1 (ko) |
| FR (1) | FR2648266B1 (ko) |
| GB (1) | GB2232496B (ko) |
| IT (1) | IT1248750B (ko) |
| NL (1) | NL194812C (ko) |
| RU (1) | RU2084972C1 (ko) |
| SE (1) | SE512452C2 (ko) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05128899A (ja) * | 1991-10-29 | 1993-05-25 | Mitsubishi Electric Corp | 半導体記憶装置 |
| AU2003207364A1 (en) * | 2002-02-26 | 2003-09-09 | Koninklijke Philips Electronics N.V. | Non-volatile memory test structure and method |
| CN107430881B (zh) * | 2015-03-09 | 2021-03-23 | 东芝存储器株式会社 | 半导体存储装置 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59185097A (ja) * | 1983-04-04 | 1984-10-20 | Oki Electric Ind Co Ltd | 自己診断機能付メモリ装置 |
| JPS62229599A (ja) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | 不揮発性半導体記憶装置 |
| EP0253161B1 (en) * | 1986-06-25 | 1991-10-16 | Nec Corporation | Testing circuit for random access memory device |
| KR910001534B1 (ko) * | 1986-09-08 | 1991-03-15 | 가부시키가이샤 도시바 | 반도체기억장치 |
| JPS6446300A (en) * | 1987-08-17 | 1989-02-20 | Nippon Telegraph & Telephone | Semiconductor memory |
| JPH01113999A (ja) * | 1987-10-28 | 1989-05-02 | Toshiba Corp | 不揮発性メモリのストレステスト回路 |
-
1989
- 1989-06-10 KR KR1019890008002A patent/KR920001080B1/ko not_active IP Right Cessation
-
1990
- 1990-02-01 FR FR9001203A patent/FR2648266B1/fr not_active Expired - Lifetime
- 1990-02-02 JP JP02022322A patent/JP3101953B2/ja not_active Expired - Fee Related
- 1990-02-02 DE DE4003132A patent/DE4003132A1/de active Granted
- 1990-02-02 NL NL9000261A patent/NL194812C/nl not_active IP Right Cessation
- 1990-02-02 GB GB9002396A patent/GB2232496B/en not_active Expired - Lifetime
- 1990-06-06 SE SE9002030A patent/SE512452C2/sv unknown
- 1990-06-07 IT IT02056690A patent/IT1248750B/it active IP Right Grant
- 1990-06-08 RU SU904830256A patent/RU2084972C1/ru not_active IP Right Cessation
- 1990-06-09 CN CN90104915A patent/CN1019243B/zh not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JP3101953B2 (ja) | 2000-10-23 |
| GB2232496A (en) | 1990-12-12 |
| CN1048463A (zh) | 1991-01-09 |
| GB2232496B (en) | 1993-06-02 |
| SE512452C2 (sv) | 2000-03-20 |
| KR910001779A (ko) | 1991-01-31 |
| GB9002396D0 (en) | 1990-04-04 |
| FR2648266A1 (fr) | 1990-12-14 |
| IT9020566A0 (ko) | 1990-06-07 |
| DE4003132C2 (ko) | 1992-06-04 |
| DE4003132A1 (de) | 1990-12-20 |
| CN1019243B (zh) | 1992-11-25 |
| FR2648266B1 (fr) | 1993-12-24 |
| NL194812B (nl) | 2002-11-01 |
| SE9002030D0 (sv) | 1990-06-06 |
| SE9002030L (sv) | 1990-12-11 |
| KR920001080B1 (ko) | 1992-02-01 |
| IT9020566A1 (it) | 1991-12-07 |
| JPH0312100A (ja) | 1991-01-21 |
| NL9000261A (nl) | 1991-01-02 |
| RU2084972C1 (ru) | 1997-07-20 |
| NL194812C (nl) | 2003-03-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970626 |