IT1185741B - Sistema di gestione di memoria di elaboratore - Google Patents

Sistema di gestione di memoria di elaboratore

Info

Publication number
IT1185741B
IT1185741B IT22962/85A IT2296285A IT1185741B IT 1185741 B IT1185741 B IT 1185741B IT 22962/85 A IT22962/85 A IT 22962/85A IT 2296285 A IT2296285 A IT 2296285A IT 1185741 B IT1185741 B IT 1185741B
Authority
IT
Italy
Prior art keywords
management system
memory management
processor memory
processor
memory
Prior art date
Application number
IT22962/85A
Other languages
English (en)
Other versions
IT8522962A0 (it
Inventor
Boleslav Sykora
Original Assignee
Mitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corp filed Critical Mitel Corp
Publication of IT8522962A0 publication Critical patent/IT8522962A0/it
Application granted granted Critical
Publication of IT1185741B publication Critical patent/IT1185741B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
IT22962/85A 1985-05-28 1985-11-22 Sistema di gestione di memoria di elaboratore IT1185741B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000482566A CA1234224A (en) 1985-05-28 1985-05-28 Computer memory management system

Publications (2)

Publication Number Publication Date
IT8522962A0 IT8522962A0 (it) 1985-11-22
IT1185741B true IT1185741B (it) 1987-11-12

Family

ID=4130575

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22962/85A IT1185741B (it) 1985-05-28 1985-11-22 Sistema di gestione di memoria di elaboratore

Country Status (8)

Country Link
US (1) US4860252A (it)
JP (1) JPS61273649A (it)
CN (1) CN85109307A (it)
CA (1) CA1234224A (it)
DE (1) DE3607092A1 (it)
FR (1) FR2582829A1 (it)
GB (1) GB2175716B (it)
IT (1) IT1185741B (it)

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US5265231A (en) * 1991-02-08 1993-11-23 Thinking Machines Corporation Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system
US5761479A (en) * 1991-04-22 1998-06-02 Acer Incorporated Upgradeable/downgradeable central processing unit chip computer systems
US5551012A (en) * 1991-04-22 1996-08-27 Acer Incorporated Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip
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US6360285B1 (en) 1994-06-30 2002-03-19 Compaq Computer Corporation Apparatus for determining memory bank availability in a computer system
US5909702A (en) * 1995-09-29 1999-06-01 Intel Corporation Memory address translations for programs code execution/relocation
US5860134A (en) * 1996-03-28 1999-01-12 International Business Machines Corporation Memory system with memory presence and type detection using multiplexed memory line function
US5715207A (en) * 1996-03-28 1998-02-03 International Business Machines Corporation Memory presence and type detection using multiplexed memory line function
JPH09293015A (ja) * 1996-04-24 1997-11-11 Mitsubishi Electric Corp メモリシステムおよびそれに用いられる半導体記憶装置
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US5774135A (en) * 1996-11-05 1998-06-30 Vlsi, Technology, Inc. Non-contiguous memory location addressing scheme
JP3649011B2 (ja) * 1998-01-09 2005-05-18 株式会社日立製作所 コンピュータシステム
TW591388B (en) * 2003-02-21 2004-06-11 Via Tech Inc Memory address decoding method and related apparatus by bit-pattern matching
TWI221221B (en) * 2003-02-27 2004-09-21 Via Tech Inc Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of address
WO2015116050A1 (en) 2014-01-29 2015-08-06 Hewlett-Packard Development Company, L.P. Thermal ink jet printhead
EP3896696A1 (en) 2014-01-31 2021-10-20 Hewlett-Packard Development Company, L.P. Three-dimensional addressing for memory
CN115826481B (zh) * 2023-02-09 2023-05-30 之江实验室 一种状态检测设备以及状态检测方法

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US4609986A (en) * 1984-06-14 1986-09-02 Altera Corporation Programmable logic array device using EPROM technology

Also Published As

Publication number Publication date
US4860252A (en) 1989-08-22
DE3607092A1 (de) 1986-12-04
CA1234224A (en) 1988-03-15
GB2175716B (en) 1989-07-19
FR2582829A1 (fr) 1986-12-05
GB8526597D0 (en) 1985-12-04
GB2175716A (en) 1986-12-03
CN85109307A (zh) 1986-11-26
JPS61273649A (ja) 1986-12-03
IT8522962A0 (it) 1985-11-22

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