IT1140233B - Unita' di controllo dei circuiti di interfaccia di ingresso-uscita di un elaboratore elettronico - Google Patents

Unita' di controllo dei circuiti di interfaccia di ingresso-uscita di un elaboratore elettronico

Info

Publication number
IT1140233B
IT1140233B IT24565/81A IT2456581A IT1140233B IT 1140233 B IT1140233 B IT 1140233B IT 24565/81 A IT24565/81 A IT 24565/81A IT 2456581 A IT2456581 A IT 2456581A IT 1140233 B IT1140233 B IT 1140233B
Authority
IT
Italy
Prior art keywords
input
control unit
output interface
interface circuit
circuit control
Prior art date
Application number
IT24565/81A
Other languages
English (en)
Other versions
IT8124565A0 (it
Inventor
Giorgio Campanini
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Priority to IT24565/81A priority Critical patent/IT1140233B/it
Publication of IT8124565A0 publication Critical patent/IT8124565A0/it
Priority to US06/434,337 priority patent/US4791553A/en
Priority to DE19823238826 priority patent/DE3238826A1/de
Application granted granted Critical
Publication of IT1140233B publication Critical patent/IT1140233B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
IT24565/81A 1981-10-20 1981-10-20 Unita' di controllo dei circuiti di interfaccia di ingresso-uscita di un elaboratore elettronico IT1140233B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT24565/81A IT1140233B (it) 1981-10-20 1981-10-20 Unita' di controllo dei circuiti di interfaccia di ingresso-uscita di un elaboratore elettronico
US06/434,337 US4791553A (en) 1981-10-20 1982-10-14 Control unit of input-output interface circuits in an electronic processor
DE19823238826 DE3238826A1 (de) 1981-10-20 1982-10-20 Steuereinheit fuer die eingabe/ausgabe-interface-schaltungen eines rechners

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT24565/81A IT1140233B (it) 1981-10-20 1981-10-20 Unita' di controllo dei circuiti di interfaccia di ingresso-uscita di un elaboratore elettronico

Publications (2)

Publication Number Publication Date
IT8124565A0 IT8124565A0 (it) 1981-10-20
IT1140233B true IT1140233B (it) 1986-09-24

Family

ID=11213997

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24565/81A IT1140233B (it) 1981-10-20 1981-10-20 Unita' di controllo dei circuiti di interfaccia di ingresso-uscita di un elaboratore elettronico

Country Status (3)

Country Link
US (1) US4791553A (it)
DE (1) DE3238826A1 (it)
IT (1) IT1140233B (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE1001383A7 (fr) * 1987-12-07 1989-10-17 Electronique Et Telecomm Bell Dispositif a acces multiples.
US5218703A (en) * 1988-07-07 1993-06-08 Siemens Aktiengesellschaft Circuit configuration and method for priority selection of interrupts for a microprocessor
US5202964A (en) * 1990-10-26 1993-04-13 Rolm Systems Interface controller including messaging scanner accessing state action table
JP2652998B2 (ja) * 1991-04-15 1997-09-10 日本電気株式会社 割込回路
US5548762A (en) * 1992-01-30 1996-08-20 Digital Equipment Corporation Implementation efficient interrupt select mechanism
JP3190748B2 (ja) * 1992-11-19 2001-07-23 エヌイーシーマイクロシステム株式会社 Ｒａｍスキャン装置
US5987537A (en) * 1997-04-30 1999-11-16 Compaq Computer Corporation Function selector with external hard wired button array on computer chassis that generates interrupt to system processor
JP3276307B2 (ja) * 1997-06-11 2002-04-22 矢崎総業株式会社 送信権の管理方法及び通信システム
DE19731634A1 (de) * 1997-07-23 1999-01-28 Nokia Telecommunications Oy Vorrichtung und Verfahren zum Auffinden einer einer Quelle zugeordneten Unterbrechungsanforderung
JP4803893B2 (ja) * 2001-03-30 2011-10-26 富士通テン株式会社 計測制御装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3432813A (en) * 1966-04-19 1969-03-11 Ibm Apparatus for control of a plurality of peripheral devices
US3434111A (en) * 1966-06-29 1969-03-18 Electronic Associates Program interrupt system
US3665415A (en) * 1970-04-29 1972-05-23 Honeywell Inf Systems Data processing system with program interrupt priority apparatus utilizing working store for multiplexing interrupt requests
US3848233A (en) * 1971-11-01 1974-11-12 Bunker Ramo Method and apparatus for interfacing with a central processing unit
US3831151A (en) * 1973-04-04 1974-08-20 Gte Automatic Electric Lab Inc Sense line processor with priority interrupt arrangement for data processing systems
IT988956B (it) * 1973-06-12 1975-04-30 Olivetti & Co Spa Governo multiplo
IT998437B (it) * 1973-08-22 1976-01-20 Honeywell Inf Systems Sistema di accesso a scansione ciclica variabile delle richieste di interruzione
IT1002275B (it) * 1973-12-27 1976-05-20 Honeywell Inf Systems Sistema di elaborazione dati a piu canali di ingresso uscita a risorse orientate per livelli di servizio distinti e interrompi bili
US4034349A (en) * 1976-01-29 1977-07-05 Sperry Rand Corporation Apparatus for processing interrupts in microprocessing systems
US4056847A (en) * 1976-08-04 1977-11-01 Rca Corporation Priority vector interrupt system
US4159518A (en) * 1977-07-05 1979-06-26 International Business Machines Corporation Auto-selection priority circuits for plural channel adapters
US4177515A (en) * 1977-12-23 1979-12-04 Ncr Corporation Interrupt adapter for data processing systems
US4315314A (en) * 1977-12-30 1982-02-09 Rca Corporation Priority vectored interrupt having means to supply branch address directly
US4261034A (en) * 1979-07-02 1981-04-07 Computer Automation, Inc. Remote distributed interrupt control for computer peripherals
US4470111A (en) * 1979-10-01 1984-09-04 Ncr Corporation Priority interrupt controller
FR2482331B1 (fr) * 1980-05-06 1986-03-21 Thomson Csf Mat Tel Procede d'arbitration centralisee, et arbitreur centralise pour systeme multiprocesseur

Also Published As

Publication number Publication date
DE3238826C2 (it) 1991-01-03
IT8124565A0 (it) 1981-10-20
DE3238826A1 (de) 1983-05-05
US4791553A (en) 1988-12-13

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