IT1209283B - Disposizione circuitale per simulare le unita' periferiche di un elaboratore elettronico. - Google Patents

Disposizione circuitale per simulare le unita' periferiche di un elaboratore elettronico.

Info

Publication number
IT1209283B
IT1209283B IT8026228A IT2622880A IT1209283B IT 1209283 B IT1209283 B IT 1209283B IT 8026228 A IT8026228 A IT 8026228A IT 2622880 A IT2622880 A IT 2622880A IT 1209283 B IT1209283 B IT 1209283B
Authority
IT
Italy
Prior art keywords
simulate
electronic processor
peripheral units
circuit provision
provision
Prior art date
Application number
IT8026228A
Other languages
English (en)
Other versions
IT8026228A0 (it
Inventor
Mariagrazia Corti
Mario Landi
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Priority to IT8026228A priority Critical patent/IT1209283B/it
Publication of IT8026228A0 publication Critical patent/IT8026228A0/it
Priority to FR8121667A priority patent/FR2494869A1/fr
Priority to DE19813146969 priority patent/DE3146969A1/de
Priority to GB8135673A priority patent/GB2093235A/en
Application granted granted Critical
Publication of IT1209283B publication Critical patent/IT1209283B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
IT8026228A 1980-11-26 1980-11-26 Disposizione circuitale per simulare le unita' periferiche di un elaboratore elettronico. IT1209283B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8026228A IT1209283B (it) 1980-11-26 1980-11-26 Disposizione circuitale per simulare le unita' periferiche di un elaboratore elettronico.
FR8121667A FR2494869A1 (fr) 1980-11-26 1981-11-19 Dispositif de circuit pour simuler les unites peripheriques d'un ordinateur electronique
DE19813146969 DE3146969A1 (de) 1980-11-26 1981-11-26 Schaltungsanordnung zum simulieren von peripheren einheiten
GB8135673A GB2093235A (en) 1980-11-26 1981-11-26 Improvements in or relating to circuit arrangements for simulating peripheral units of electronic processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8026228A IT1209283B (it) 1980-11-26 1980-11-26 Disposizione circuitale per simulare le unita' periferiche di un elaboratore elettronico.

Publications (2)

Publication Number Publication Date
IT8026228A0 IT8026228A0 (it) 1980-11-26
IT1209283B true IT1209283B (it) 1989-07-16

Family

ID=11218997

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8026228A IT1209283B (it) 1980-11-26 1980-11-26 Disposizione circuitale per simulare le unita' periferiche di un elaboratore elettronico.

Country Status (4)

Country Link
DE (1) DE3146969A1 (it)
FR (1) FR2494869A1 (it)
GB (1) GB2093235A (it)
IT (1) IT1209283B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05216712A (ja) * 1991-10-23 1993-08-27 Internatl Business Mach Corp <Ibm> コンピュータシステムおよびこのコンピュータシステム上で内観的タスクを遂行する方法並びにｉ／ｏプロセッサアセンブリ

Also Published As

Publication number Publication date
GB2093235A (en) 1982-08-25
DE3146969A1 (de) 1982-11-18
IT8026228A0 (it) 1980-11-26
FR2494869A1 (fr) 1982-05-28

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