GB2093235A - Improvements in or relating to circuit arrangements for simulating peripheral units of electronic processors - Google Patents

Abstract

A circuit arrangement SP for simulating peripheral units of an electronic processor is controlled or monitored by a microprocessor MP. The circuit arrangement comprises interface circuits SIND, SINP, equal in number to the number of interface circuits present in an input-output module being tested, enabled by a selection circuit DEP. A bidirectional data bus BDB connects together the microprocessor, the selection circuit of the interface circuits, and units SIP, SID, SOUT for data exchange between the interface circuits and the microprocessor. A first unidirectional bus BC is managed by a first exchange unit SOUT and carries data from the data bus for the interface circuits. A second unidirectional bus BD is managed by a second exchange circuit SID and carries data for the data bus from the interface circuits SIND that physically occupy the even positions. A third unidirectional bus BP is managed by a third exchange circuit SIP which carries data to the data bus from the interface circuits SINP that physically occupy odd positions. <IMAGE>

Description

SPECIFICATION Improvements in or relating to circuit arrangements for simulating peripheral units of electronic processors.

The present invention relates to a circuit arrangement for simulating peripheral units connected to interface circuits of an input-output module of an electronic processor. A processor or calculator may be connected to a plurality of peripheral units which may differ tremendously from each other as far as their individual characteristics are connected (transmission speed, serial or parallel transmission, code used, etc).

For example,the following peripheral units may be present, teleprinters, card, punched-tape or magnetic tape readers, slow or high speed printers, data terminals, card or tape perforators, etc. The interface circuits of a processor are often grouped into functional units, called modules, which also comprise supervising and management circuits of the connection between interface circuits and peripheral units.

For every type of peripheral unit that may be connected to the electronic processor, there corresponds an interface circuit having specific characteristics. Thus, it follows that the electrical characteristics of the electrical characteristics of the input-output modules of the same processor also differ from each other, being correlated to those of the interface circuits that make up each module.

This non-uniformity can cause problems and extra cost as far as the development and testing of the input-output modules is concerned, perhaps requiring the physical presence of the peripheral units to be connected to each module in order to carry out both the necessary tests during the course of development and the final test at the production stage. This can both be expensive and cause problems, including logistical ones, of no small importance.

According to the invention, there is provided a circuit arrangement for simulating peripheral units of an electronic processor, comprising: a microprocessor; a plurality of interface circuits arranged to be enabled by a selection circuit; a bidirectional data bus interconnecting the microprocessor, the selection ciruit and interexchange units arranged to manage dialogue between the interface circuits and the microprocessor; a first unidirectional bus, arranged to be managed by a first of the interexchange units, along with data from the data bus for the interface circuits pass; and at least one second unidirectional bus, arranged to be managed by a respective second of the inter-exchange units, along which data for the data bus from the interface circuits pass.

It is thus possible to provide a circuit arrangement which may be connected to the interface circuits of a module to simuate the electrical behaviour of the peripheral units to which the module is to be connected. Such a circuit arrangement may be microprogrammed so as to be easily adaptable to the electrical characteristics required by the module under test.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a preferred embodiment of the invention; and Figure 2 schematically shows a possible use of the invention for testing an input-output module.

Figure 1 is a block diagram of a peripheral unit simulator SP constituting a preferrred embodiment of the invention. In the drawing, MP indicates a microprocessor which superintends the correct operation of the simulator SP. The microprocessor MP is connected by means of a bi- directional bus BDB to a unit DEP for the selection of the interface circuits (SINP, SIND), to a first inter-exchange circuit SOUT which manages the passage of data from the bidirectional bus BDB for an interface circuit, and to at least one second inter-exchange circuit (SIP, SID) which manages the passage of the data from an interface circuit for the bidirectional bus BDB.

In Figure 1, there is schematically shown a peripheral unit simulator SP which is suitable for connection to a module comprising interface circuits (like the one described, for example, in Italian patent application No. 24283A/80 of the 26/8/1 980) and for verifying that two of the interface circuits, which are adjacent and connected to peripheral units for performing the same functions at the same time, operate in synchronism (link procedure).

For this purpose the interface circuits of the simulator SP are defined, on the basis of their physical position, "even" and "odd" and the simulator comprises two second interexchange circuits SIP and SID to which are supplied by means of two distinct unidirectional buses BP and BD respectively, data from the "even" interface circuits SINP and the "odd" circuits SIND respectively. Therefore the simulator SP is able to acquire and manage at the same time the data from the two adjacent interfaces operating in the link mode.

The data from the bidirectional bus BDB, and which is managed by the first inter-exchange circuit SOUT, are supplied to all the interface circuits SIND, SINP by means of another unidirectional bus BC.

If the module does not include interface circuits designed to operate in the link mode, there is no reason for the distinction between "even" and "odd" interface circuits to subsist in the simulator and all the interface circuits send data to a single second inter-exchange circuit by means of a single unidirectional bus.

The address of the interface to be selected is sent by the microprocessor MP, by means of the bus BDB, to the circuit DEP where it is stored in a control register RC and afterwards sent to a decoder DEC which activates one of the enabling lines AB of the interface circuits (SIND, SINP). For reliability reasons the address is sent to two decoders DEC the outputs of which are connected to a comparing circuit CO which, if a difference is detected, generates an error signal stored (together with error signals E generated by other circuits which for the sake of simplicity are not shown in the drawings) in the status or condition register RS.

The data sent by the microprocessor MP to the interface circuits in parallel on the bus BDB are supplied to the first inter-exchange circuit SOUT, and via a parallel-series-converter P/S and a parity generating circuit GP and a bus BC in serial mode to the interface circuit SIND, SINP enabled by the circuit DEP by means of the corresponding line AB.

The interface circuits SIND, SINP include linedrivers and line receivers, which are necessary for the exchange of data with the interface INT of the module to which they are connected, respective enabling circuits controlled by the circuit DEP through the respective lines AB, and, in a possible form of realization, parity controlling circuits the error signal of which can be one of the signals, generically indicated by E, stored in the condition register RS of the first (SOUT) or second (SIP or SID) inter-exchange circuit).

The instructions sent by the microprocessor and stored in the control registers RC have been generically indicated in Figure 1 by C The second inter-exchange circuit SID or SIP receives the data from the interface circuit SIND or SINP, via the bus BD or BP. After a series-parallel conversion performed by the converter S/P, the circuit CP carries out a parity control or check. Any error is stored in the condition register RS together with the other error signals (generically indicated by E) generated by the control or autocontrol circuits with which the inter-exchange circuit is provided and which, for simplicity, have been omitted.

In the embodiment shown in Figure 1, only the circuit SID is provided with a control register RC, in which the instructions sent by the microprocessor MP and relating to the circuit SIP are also stored. However, the circuit SIP may also be provided with a control register RC.

By acting upon a multiplexers MPX, the microprocessor MP can receive, via the bus BDB, the contents of the status or condition register RS or the data from the interface circuits (SIND or SINP).

As already mentioned, the peripheral unit simulator SP may be advantageously utilized for the final testing of a module. Therefore, the ability to check the operation of the peripheral unit simulator SP may be of particular importance.

The means adopted for this purpose are those often used in the field of electronic processors and, by way of example, may include the following: the duplicating of the decoding circuit DEC and the control or check circuit CO present in the circuit DEP; the possibility of transcribing (upon command or instruction of the microprocessor MP) the contents of the control register RC into the condition register RS (if the registers and the bus BDB are operating correctly, the command word written by the microprocessor MP in the control register RC returns to it unchanged as a condition of status word from the condition register RS); and the possibility of connecting the inputs of the line-drivers to the output of the line-receivers in the interface circuits SIND, SINP, thus verifying the correct operation of the transmission buses and of the circuits concerned with the data flow.

Furthermore, the microprocessor MP has the ability to introduce errors, including formal ones (for example of parity) into the data flow transmitted to the interface circuits (SIND, SINP, as well as to delay or suppress the sending of reply signals. This is very useful during the testing stage of an input-output module for checking the operation of the control or checking circuits of the module itself.

Often the testing procedure is managed by a test processor EP. Therefore, the peripheral unit simulator SP comprises a specialized interface circuit ESI which allows the processor EP to have access to the bidirectional bus BDB.

In Figure 2 the use of a peripheral unit simulator SP to test an input-output module of an electornic processor EL is schematically indicated.

The module MOP under test is inserted in the processor EL in the same way as other modules MO, and is connected by means of n-bidirectional connections, equal in number to the number of interface circuits INT provided in the module MOP, to the peripheral unit simulator SP.

The testing processor EP dialogues with the simulator SP, and with a circuit TCC for managing the exchange of data between an external processor and a remote control circuit CON (that in its turn dialogues with the CPU) and/or the input-output modules MO of the processor EL.

The circuit TCC may be that described in Italian patent application No. 24284 A/80 of the 26/8/1980.

Claims (4)

1. A circuit arrangement for simulating peripheral units of an electronic processor, comprising: a microprocessor; a plurality of interface circuits arranged to be enabled by a selection circuit; a bidirectional data bus interconnecting the microprocessor, the selection circuit and inter-exchange units arranged to manage dialogue between the interface circuits and the microprocessor; a first unidirectional bus arranged to be managed by a first of the interexchange units, along which data from the data bus for the interface circuits pass; and at least one second unidirectional bus arranged to be managed by a respective second of the inter-exchange units, along which data for the data bus from the interface circuits pass.

2. A circuit arrangement as claimed in ciaim 1, arranged to dialogue with an electronic processor which has access to the data bus through a further interface circuit of the circuit arrangement.

3. A circuit arrangement as claimed in claim 1 or 2, in wich a first group of the interface circuits which physically occupy "odd" positions are connected to each other by an "odd" second bus, a second group of the interface circuits which occupy "even" positions are connected to each other by an "even" second bus, and "odd" and "even" second inter-exchange untis are arranged to manage, the "odd" and "even" second buses, respectively.

4. A circuit arrangement for simulating peripheral units of an electronic processor, substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.