IT1135748B - Transistor a effetto di campo a canale corto - Google Patents

Transistor a effetto di campo a canale corto

Info

Publication number
IT1135748B
IT1135748B IT21239/81A IT2123981A IT1135748B IT 1135748 B IT1135748 B IT 1135748B IT 21239/81 A IT21239/81 A IT 21239/81A IT 2123981 A IT2123981 A IT 2123981A IT 1135748 B IT1135748 B IT 1135748B
Authority
IT
Italy
Prior art keywords
short
effect transistor
channel field
channel
field
Prior art date
Application number
IT21239/81A
Other languages
English (en)
Italian (it)
Other versions
IT8121239A0 (it
Inventor
Martin Paul Lepselter
Simon Min Sze
Hyman Joseph Levinstein
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/141,120 external-priority patent/US4343082A/en
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of IT8121239A0 publication Critical patent/IT8121239A0/it
Application granted granted Critical
Publication of IT1135748B publication Critical patent/IT1135748B/it

Links

Classifications

    • H01L29/66575—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L29/41783—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
IT21239/81A 1980-04-17 1981-04-16 Transistor a effetto di campo a canale corto IT1135748B (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14112180A 1980-04-17 1980-04-17
US06/141,120 US4343082A (en) 1980-04-17 1980-04-17 Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device

Publications (2)

Publication Number Publication Date
IT8121239A0 IT8121239A0 (it) 1981-04-16
IT1135748B true IT1135748B (it) 1986-08-27

Family

ID=26838805

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21239/81A IT1135748B (it) 1980-04-17 1981-04-16 Transistor a effetto di campo a canale corto

Country Status (5)

Country Link
DE (1) DE3115596A1 (ja)
FR (1) FR2481005A1 (ja)
GB (1) GB2074374B (ja)
IT (1) IT1135748B (ja)
NL (1) NL8101902A (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1197926A (en) * 1981-12-16 1985-12-10 William D. Ryden Zero drain overlap and self-aligned contacts and contact methods for mod devices
DE3211761A1 (de) * 1982-03-30 1983-10-06 Siemens Ag Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen
FR2525029A1 (fr) * 1982-04-08 1983-10-14 Commissariat Energie Atomique Procede d'isolation d'une ligne conductrice dans un circuit integre et procede de fabrication d'un transistor mos utilisant un tel procede d'isolation
US4485550A (en) * 1982-07-23 1984-12-04 At&T Bell Laboratories Fabrication of schottky-barrier MOS FETs
JPS59106172A (ja) * 1982-12-07 1984-06-19 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 電界効果トランジスタの製造方法
JPS59210642A (ja) * 1983-05-16 1984-11-29 Hitachi Ltd 半導体装置の製造方法
US4453306A (en) * 1983-05-27 1984-06-12 At&T Bell Laboratories Fabrication of FETs

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS

Also Published As

Publication number Publication date
GB2074374A (en) 1981-10-28
NL8101902A (nl) 1981-11-16
GB2074374B (en) 1984-04-26
FR2481005A1 (fr) 1981-10-23
DE3115596A1 (de) 1982-04-01
DE3115596C2 (ja) 1988-04-14
IT8121239A0 (it) 1981-04-16
FR2481005B1 (ja) 1983-10-21

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