IT1028309B - Struttura di sipositivo a circuito integrato isolata con ossido e procedimento per la sua fabbricazione - Google Patents

Struttura di sipositivo a circuito integrato isolata con ossido e procedimento per la sua fabbricazione

Info

Publication number
IT1028309B
IT1028309B IT1919175A IT1919175A IT1028309B IT 1028309 B IT1028309 B IT 1028309B IT 1919175 A IT1919175 A IT 1919175A IT 1919175 A IT1919175 A IT 1919175A IT 1028309 B IT1028309 B IT 1028309B
Authority
IT
Italy
Prior art keywords
sipositive
procedure
oxide
manufacturing
integrated circuit
Prior art date
Application number
IT1919175A
Other languages
English (en)
Italian (it)
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Application granted granted Critical
Publication of IT1028309B publication Critical patent/IT1028309B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT1919175A 1974-01-14 1975-01-10 Struttura di sipositivo a circuito integrato isolata con ossido e procedimento per la sua fabbricazione IT1028309B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US43289674A 1974-01-14 1974-01-14

Publications (1)

Publication Number Publication Date
IT1028309B true IT1028309B (it) 1979-01-30

Family

ID=23718017

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1919175A IT1028309B (it) 1974-01-14 1975-01-10 Struttura di sipositivo a circuito integrato isolata con ossido e procedimento per la sua fabbricazione

Country Status (7)

Country Link
JP (1) JPS50104579A (fr)
CA (1) CA1010157A (fr)
DE (1) DE2500867A1 (fr)
FR (1) FR2258001B1 (fr)
GB (1) GB1485183A (fr)
IT (1) IT1028309B (fr)
NL (1) NL7500360A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2605641C3 (de) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Hochfrequenztransistor und Verfahren zu seiner Herstellung
FR2470444A1 (fr) * 1979-11-21 1981-05-29 Radiotechnique Compelec Perfectionnement au procede de realisation d'un reseau de connexions par anodisation localisee sur un support semi-conducteur

Also Published As

Publication number Publication date
NL7500360A (nl) 1975-07-16
JPS50104579A (fr) 1975-08-18
FR2258001B1 (fr) 1978-08-25
GB1485183A (en) 1977-09-08
FR2258001A1 (fr) 1975-08-08
DE2500867A1 (de) 1975-07-24
CA1010157A (en) 1977-05-10

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