IN2014DN10143A - - Google Patents
Info
- Publication number
- IN2014DN10143A IN2014DN10143A IN10143DEN2014A IN2014DN10143A IN 2014DN10143 A IN2014DN10143 A IN 2014DN10143A IN 10143DEN2014 A IN10143DEN2014 A IN 10143DEN2014A IN 2014DN10143 A IN2014DN10143 A IN 2014DN10143A
- Authority
- IN
- India
- Prior art keywords
- gan
- wafers
- substrate
- ammophilic
- render
- Prior art date
Links
- 235000012431 wafers Nutrition 0.000 abstract 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract 1
- 229910021529 ammonia Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Led Devices (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/484,542 US8796054B2 (en) | 2012-05-31 | 2012-05-31 | Gallium nitride to silicon direct wafer bonding |
PCT/US2013/042380 WO2013181053A1 (fr) | 2012-05-31 | 2013-05-23 | Liaison de tranche directe entre du nitrure de gallium et du silicium |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2014DN10143A true IN2014DN10143A (fr) | 2015-08-21 |
Family
ID=49669153
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN10143DEN2014 IN2014DN10143A (fr) | 2012-05-31 | 2013-05-23 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8796054B2 (fr) |
EP (1) | EP2859592B1 (fr) |
CN (1) | CN104471726B (fr) |
IN (1) | IN2014DN10143A (fr) |
TW (1) | TWI597800B (fr) |
WO (1) | WO2013181053A1 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9690042B2 (en) | 2013-05-23 | 2017-06-27 | Electronics And Telecommunications Research Institute | Optical input/output device, optical electronic system including the same, and method of manufacturing the same |
JP6176069B2 (ja) * | 2013-11-13 | 2017-08-09 | 住友電気工業株式会社 | Iii族窒化物複合基板およびその製造方法、積層iii族窒化物複合基板、ならびにiii族窒化物半導体デバイスおよびその製造方法 |
CN103887379B (zh) * | 2014-03-28 | 2017-04-19 | 西安神光皓瑞光电科技有限公司 | 用湿法腐蚀减少GaN外延缺陷的方法 |
FR3029352B1 (fr) * | 2014-11-27 | 2017-01-06 | Soitec Silicon On Insulator | Procede d'assemblage de deux substrats |
DE102015103323A1 (de) * | 2015-03-06 | 2016-09-08 | Infineon Technologies Austria Ag | Verfahren zum Herstellen von Halbleitervorrichtungen durch Bonden einer Halbleiterscheibe auf ein Basissubstrat, zusammengesetzter Wafer und Halbleitervorrichtung |
TWI645479B (zh) * | 2015-05-13 | 2018-12-21 | 財團法人工業技術研究院 | 貼合結構、其製造方法及晶粒結構 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1988109B (zh) * | 2005-12-21 | 2012-03-21 | 弗赖贝格化合物原料有限公司 | 生产自支撑iii-n层和自支撑iii-n基底的方法 |
JP4756418B2 (ja) | 2006-02-28 | 2011-08-24 | 公立大学法人大阪府立大学 | 単結晶窒化ガリウム基板の製造方法 |
JP2008004821A (ja) * | 2006-06-23 | 2008-01-10 | Sumco Corp | 貼り合わせウェーハの製造方法 |
US7811900B2 (en) | 2006-09-08 | 2010-10-12 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a thick layer transfer process |
CN101960604B (zh) | 2008-03-13 | 2013-07-10 | S.O.I.Tec绝缘体上硅技术公司 | 绝缘隐埋层中有带电区的衬底 |
TWI492275B (zh) * | 2008-04-10 | 2015-07-11 | Shinetsu Chemical Co | The method of manufacturing the bonded substrate |
US8692260B2 (en) | 2008-09-26 | 2014-04-08 | Soitec | Method of forming a composite laser substrate |
US8551862B2 (en) | 2009-01-15 | 2013-10-08 | Shin-Etsu Chemical Co., Ltd. | Method of manufacturing laminated wafer by high temperature laminating method |
JP2010192872A (ja) * | 2009-01-23 | 2010-09-02 | Sumitomo Electric Ind Ltd | 半導体基板の製造方法、半導体デバイスの製造方法、半導体基板および半導体デバイス |
US8367519B2 (en) * | 2009-12-30 | 2013-02-05 | Memc Electronic Materials, Inc. | Method for the preparation of a multi-layered crystalline structure |
US8440541B2 (en) * | 2010-02-25 | 2013-05-14 | Memc Electronic Materials, Inc. | Methods for reducing the width of the unbonded region in SOI structures |
-
2012
- 2012-05-31 US US13/484,542 patent/US8796054B2/en not_active Expired - Fee Related
-
2013
- 2013-05-23 CN CN201380029045.5A patent/CN104471726B/zh not_active Expired - Fee Related
- 2013-05-23 EP EP13796280.9A patent/EP2859592B1/fr not_active Not-in-force
- 2013-05-23 WO PCT/US2013/042380 patent/WO2013181053A1/fr active Application Filing
- 2013-05-23 IN IN10143DEN2014 patent/IN2014DN10143A/en unknown
- 2013-05-24 TW TW102118516A patent/TWI597800B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP2859592B1 (fr) | 2018-09-26 |
WO2013181053A1 (fr) | 2013-12-05 |
TWI597800B (zh) | 2017-09-01 |
TW201405702A (zh) | 2014-02-01 |
US8796054B2 (en) | 2014-08-05 |
EP2859592A1 (fr) | 2015-04-15 |
CN104471726A (zh) | 2015-03-25 |
EP2859592A4 (fr) | 2016-03-02 |
US20130320404A1 (en) | 2013-12-05 |
CN104471726B (zh) | 2018-01-09 |
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