IN189112B - - Google Patents

Info

Publication number
IN189112B
IN189112B IN985CA1996A IN189112B IN 189112 B IN189112 B IN 189112B IN 985CA1996 A IN985CA1996 A IN 985CA1996A IN 189112 B IN189112 B IN 189112B
Authority
IN
India
Application number
Other languages
English (en)
Inventor
Frank Dr Lau
Wolfgang Dr Kreutschneider
Manfred Dr Engelhardt
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of IN189112B publication Critical patent/IN189112B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/763Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
IN985CA1996 1995-07-10 1996-05-30 IN189112B (forum.php)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19525072A DE19525072C2 (de) 1995-07-10 1995-07-10 Integrierte Schaltungsanordnung, bei der ein erstes Bauelement an einer Hauptfläche eines Halbleitersubstrats und ein zweites Bauelement am Grabenboden angeordnet sind, und Verfahren zu deren Herstellung

Publications (1)

Publication Number Publication Date
IN189112B true IN189112B (forum.php) 2002-12-21

Family

ID=7766444

Family Applications (1)

Application Number Title Priority Date Filing Date
IN985CA1996 IN189112B (forum.php) 1995-07-10 1996-05-30

Country Status (9)

Country Link
US (1) US5990536A (forum.php)
EP (1) EP0838089B1 (forum.php)
JP (1) JPH11509043A (forum.php)
KR (1) KR100418849B1 (forum.php)
CN (1) CN1093983C (forum.php)
AR (1) AR002791A1 (forum.php)
DE (2) DE19525072C2 (forum.php)
IN (1) IN189112B (forum.php)
WO (1) WO1997003463A1 (forum.php)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218720B1 (en) * 1998-10-21 2001-04-17 Advanced Micro Devices, Inc. Semiconductor topography employing a nitrogenated shallow trench isolation structure
US7071043B2 (en) * 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134445A (ja) * 1982-02-05 1983-08-10 Seiko Epson Corp 半導体装置の製造方法
JPS58169934A (ja) * 1982-03-30 1983-10-06 Fujitsu Ltd 半導体集積回路装置
JPS61135151A (ja) * 1984-12-05 1986-06-23 Mitsubishi Electric Corp 半導体記憶装置
US5176789A (en) * 1985-09-21 1993-01-05 Semiconductor Energy Laboratory Co., Ltd. Method for depositing material on depressions
JPS6378573A (ja) * 1986-09-22 1988-04-08 Hitachi Ltd 半導体装置
US4835584A (en) * 1986-11-27 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Trench transistor
DE3809218C2 (de) * 1987-03-20 1994-09-01 Mitsubishi Electric Corp Halbleitereinrichtung mit einem Graben und Verfahren zum Herstellen einer solchen Halbleitereinrichtung
JPH0620108B2 (ja) * 1987-03-23 1994-03-16 三菱電機株式会社 半導体装置の製造方法
US4977436A (en) * 1988-07-25 1990-12-11 Motorola, Inc. High density DRAM
JPH04151850A (ja) * 1990-10-15 1992-05-25 Nec Corp 溝絶縁分離型半導体集積回路の製造方法
FR2672731A1 (fr) * 1991-02-07 1992-08-14 France Telecom Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant.
US5122848A (en) * 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
EP0540262A2 (en) * 1991-10-31 1993-05-05 STMicroelectronics, Inc. Trench isolation region
JPH0637275A (ja) * 1992-07-13 1994-02-10 Toshiba Corp 半導体記憶装置及びその製造方法
US5512517A (en) * 1995-04-25 1996-04-30 International Business Machines Corporation Self-aligned gate sidewall spacer in a corrugated FET and method of making same

Also Published As

Publication number Publication date
US5990536A (en) 1999-11-23
JPH11509043A (ja) 1999-08-03
KR100418849B1 (ko) 2004-04-21
EP0838089A1 (de) 1998-04-29
DE19525072A1 (de) 1997-01-16
EP0838089B1 (de) 2001-09-19
DE19525072C2 (de) 2002-06-27
CN1190490A (zh) 1998-08-12
CN1093983C (zh) 2002-11-06
AR002791A1 (es) 1998-04-29
WO1997003463A1 (de) 1997-01-30
KR19990014889A (ko) 1999-02-25
DE59607729D1 (de) 2001-10-25

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