IL135870A - Polygon representation in an integrated circuit layout - Google Patents

Polygon representation in an integrated circuit layout

Info

Publication number
IL135870A
IL135870A IL13587098A IL13587098A IL135870A IL 135870 A IL135870 A IL 135870A IL 13587098 A IL13587098 A IL 13587098A IL 13587098 A IL13587098 A IL 13587098A IL 135870 A IL135870 A IL 135870A
Authority
IL
Israel
Prior art keywords
integrated circuit
circuit layout
polygon representation
polygon
representation
Prior art date
Application number
IL13587098A
Other languages
English (en)
Other versions
IL135870A0 (en
Original Assignee
David C Chapman
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by David C Chapman filed Critical David C Chapman
Publication of IL135870A0 publication Critical patent/IL135870A0/xx
Publication of IL135870A publication Critical patent/IL135870A/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
IL13587098A 1997-10-30 1998-10-28 Polygon representation in an integrated circuit layout IL135870A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/960,715 US6128767A (en) 1997-10-30 1997-10-30 Polygon representation in an integrated circuit layout
PCT/US1998/022819 WO1999023699A2 (en) 1997-10-30 1998-10-28 Polygon representation in an integrated circuit layout

Publications (2)

Publication Number Publication Date
IL135870A0 IL135870A0 (en) 2001-05-20
IL135870A true IL135870A (en) 2005-03-20

Family

ID=25503526

Family Applications (1)

Application Number Title Priority Date Filing Date
IL13587098A IL135870A (en) 1997-10-30 1998-10-28 Polygon representation in an integrated circuit layout

Country Status (9)

Country Link
US (1) US6128767A (xx)
EP (2) EP1044471B1 (xx)
JP (1) JP3710710B2 (xx)
KR (1) KR100399645B1 (xx)
CA (1) CA2308707C (xx)
DE (2) DE69813892T2 (xx)
IL (1) IL135870A (xx)
TW (1) TW515066B (xx)
WO (1) WO1999023699A2 (xx)

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US6957410B2 (en) 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US7024650B2 (en) * 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
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US7080336B2 (en) * 2000-12-06 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for computing placement costs
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US7096448B2 (en) * 2001-01-19 2006-08-22 Cadence Design Systems, Inc. Method and apparatus for diagonal routing by using several sets of lines
US6915501B2 (en) 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
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US6973634B1 (en) 2002-01-22 2005-12-06 Cadence Design Systems, Inc. IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6684380B2 (en) * 2002-04-01 2004-01-27 International Business Machines Corporation Intelligent structure simplification to facilitate package analysis of complex packages
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US7480885B2 (en) * 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US6996789B2 (en) * 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
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US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7096445B1 (en) 2003-01-14 2006-08-22 Cadence Design Systems, Inc. Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit
US7243328B2 (en) * 2003-05-07 2007-07-10 Cadence Design Systems, Inc. Method and apparatus for representing items in a design layout
US7100135B2 (en) * 2004-06-18 2006-08-29 Intel Corporation Method and system to evaluate signal line spacing
US7191425B1 (en) * 2004-11-18 2007-03-13 Sun Microsystems, Inc. Method and apparatus for inserting extra tracks during library architecture migration
JP4817746B2 (ja) * 2005-07-27 2011-11-16 株式会社東芝 半導体装置の設計データ処理方法、そのプログラム、及び半導体装置の製造方法
US20070220472A1 (en) * 2006-02-28 2007-09-20 Inventec Corporation Computer aided wave-shaped circuit line drawing method and system
JP4637043B2 (ja) * 2006-03-23 2011-02-23 新光電気工業株式会社 自動配線整形方法および自動配線整形装置
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US8146025B2 (en) * 2009-07-30 2012-03-27 United Microelectronics Corp. Method for correcting layout pattern using rule checking rectangle
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Also Published As

Publication number Publication date
JP3710710B2 (ja) 2005-10-26
IL135870A0 (en) 2001-05-20
CA2308707A1 (en) 1999-05-14
EP1324234A1 (en) 2003-07-02
TW515066B (en) 2002-12-21
KR100399645B1 (ko) 2003-09-29
DE69813892D1 (de) 2003-05-28
DE69813892T2 (de) 2004-02-26
EP1324234B1 (en) 2004-06-23
WO1999023699A2 (en) 1999-05-14
DE69824765T2 (de) 2005-07-21
JP2001522111A (ja) 2001-11-13
EP1044471B1 (en) 2003-04-23
CA2308707C (en) 2005-01-11
US6128767A (en) 2000-10-03
DE69824765D1 (de) 2004-07-29
WO1999023699A3 (en) 1999-07-22
KR20010031616A (ko) 2001-04-16
EP1044471A2 (en) 2000-10-18

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Legal Events

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KB Patent renewed
MM9K Patent not in force due to non-payment of renewal fees