DE69813892D1 - Polygon darstellung im layout eines integrierten schaltkreises - Google Patents

Polygon darstellung im layout eines integrierten schaltkreises

Info

Publication number
DE69813892D1
DE69813892D1 DE69813892T DE69813892T DE69813892D1 DE 69813892 D1 DE69813892 D1 DE 69813892D1 DE 69813892 T DE69813892 T DE 69813892T DE 69813892 T DE69813892 T DE 69813892T DE 69813892 D1 DE69813892 D1 DE 69813892D1
Authority
DE
Germany
Prior art keywords
layout
integrated circuit
polygon display
polygon
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69813892T
Other languages
English (en)
Other versions
DE69813892T2 (de
Inventor
David C Chapman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of DE69813892D1 publication Critical patent/DE69813892D1/de
Application granted granted Critical
Publication of DE69813892T2 publication Critical patent/DE69813892T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
DE69813892T 1997-10-30 1998-10-28 Polygon darstellung im layout eines integrierten schaltkreises Expired - Lifetime DE69813892T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/960,715 US6128767A (en) 1997-10-30 1997-10-30 Polygon representation in an integrated circuit layout
US960715 1997-10-30
PCT/US1998/022819 WO1999023699A2 (en) 1997-10-30 1998-10-28 Polygon representation in an integrated circuit layout

Publications (2)

Publication Number Publication Date
DE69813892D1 true DE69813892D1 (de) 2003-05-28
DE69813892T2 DE69813892T2 (de) 2004-02-26

Family

ID=25503526

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69813892T Expired - Lifetime DE69813892T2 (de) 1997-10-30 1998-10-28 Polygon darstellung im layout eines integrierten schaltkreises
DE69824765T Expired - Lifetime DE69824765T2 (de) 1997-10-30 1998-10-28 Polygondarstellung im Layout eines integrierten Schaltkreises

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69824765T Expired - Lifetime DE69824765T2 (de) 1997-10-30 1998-10-28 Polygondarstellung im Layout eines integrierten Schaltkreises

Country Status (9)

Country Link
US (1) US6128767A (de)
EP (2) EP1044471B1 (de)
JP (1) JP3710710B2 (de)
KR (1) KR100399645B1 (de)
CA (1) CA2308707C (de)
DE (2) DE69813892T2 (de)
IL (1) IL135870A (de)
TW (1) TW515066B (de)
WO (1) WO1999023699A2 (de)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000048052A (ja) * 1998-07-27 2000-02-18 Mitsubishi Electric Corp レイアウト検証方法とレイアウト検証装置
US6693719B1 (en) * 1998-09-16 2004-02-17 Texas Instruments Incorporated Path to trapezoid decomposition of polygons for printing files in a page description language
US6288724B1 (en) * 1998-09-16 2001-09-11 Texas Instruments Incorporated Clipping and trapezoid decomposition of polygons for printing files in a page description language
US6341366B1 (en) * 1999-01-15 2002-01-22 Spring Soft Inc. Rule-driven method and system for editing physical integrated circuit layouts
US6285805B1 (en) * 1999-01-25 2001-09-04 International Business Machines Corp. System and method for finding the distance from a moving query point to the closest point on one or more convex or non-convex shapes
JP3822009B2 (ja) * 1999-11-17 2006-09-13 株式会社東芝 自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US6826737B2 (en) * 2000-12-06 2004-11-30 Cadence Design Systems, Inc. Recursive partitioning placement method and apparatus
US7003754B2 (en) * 2000-12-07 2006-02-21 Cadence Design Systems, Inc. Routing method and apparatus that use of diagonal routes
US7055120B2 (en) * 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US6516455B1 (en) * 2000-12-06 2003-02-04 Cadence Design Systems, Inc. Partitioning placement method using diagonal cutlines
US6957410B2 (en) 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US7024650B2 (en) * 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
EP1362373A2 (de) * 2000-12-06 2003-11-19 Simplex Solutions, Inc. Verfahren und apparat mit berücksichtigung der diagonalen verdrahtung in der plazierung
US7080336B2 (en) * 2000-12-06 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for computing placement costs
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US7096448B2 (en) * 2001-01-19 2006-08-22 Cadence Design Systems, Inc. Method and apparatus for diagonal routing by using several sets of lines
US6915501B2 (en) 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US6882055B1 (en) 2001-06-03 2005-04-19 Cadence Design Systems, Inc. Non-rectilinear polygonal vias
US6957411B1 (en) 2001-06-03 2005-10-18 Cadence Design Systems, Inc. Gridless IC layout and method and apparatus for generating such a layout
US6829757B1 (en) 2001-06-03 2004-12-07 Cadence Design Systems, Inc. Method and apparatus for generating multi-layer routes
US6976238B1 (en) 2001-06-03 2005-12-13 Cadence Design Systems, Inc. Circular vias and interconnect-line ends
US7069530B1 (en) 2001-06-03 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for routing groups of paths
US6859916B1 (en) 2001-06-03 2005-02-22 Cadence Design Systems, Inc. Polygonal vias
US7107564B1 (en) 2001-06-03 2006-09-12 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6877146B1 (en) 2001-06-03 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US6895569B1 (en) 2001-06-03 2005-05-17 Candence Design Systems, Inc. IC layout with non-quadrilateral Steiner points
US7310793B1 (en) 2001-06-03 2007-12-18 Cadence Design Systems, Inc. Interconnect lines with non-rectilinear terminations
US6795958B2 (en) 2001-08-23 2004-09-21 Cadence Design Systems, Inc. Method and apparatus for generating routes for groups of related node configurations
US6931616B2 (en) * 2001-08-23 2005-08-16 Cadence Design Systems, Inc. Routing method and apparatus
US6877149B2 (en) 2001-08-23 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes
US7143382B2 (en) 2001-08-23 2006-11-28 Cadence Design Systems, Inc. Method and apparatus for storing routes
US7058913B1 (en) 2001-09-06 2006-06-06 Cadence Design Systems, Inc. Analytical placement method and apparatus
US6629304B1 (en) * 2001-09-19 2003-09-30 Lsi Logic Corporation Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells
US7159197B2 (en) * 2001-12-31 2007-01-02 Synopsys, Inc. Shape-based geometry engine to perform smoothing and other layout beautification operations
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US6944841B1 (en) 2002-01-22 2005-09-13 Cadence Design Systems, Inc. Method and apparatus for proportionate costing of vias
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US7117468B1 (en) 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US6973634B1 (en) 2002-01-22 2005-12-06 Cadence Design Systems, Inc. IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6684380B2 (en) * 2002-04-01 2004-01-27 International Business Machines Corporation Intelligent structure simplification to facilitate package analysis of complex packages
US6931615B1 (en) 2002-06-04 2005-08-16 Cadence Design Systems, Inc. Method and apparatus for identifying a path between source and target states
US7069531B1 (en) 2002-07-15 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for identifying a path between source and target states in a space with more than two dimensions
US7047512B1 (en) 2002-06-04 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space
US7058917B1 (en) 2002-06-04 2006-06-06 Cadence Design Systems, Inc. Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space
US6892369B2 (en) * 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US6988257B2 (en) * 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7171635B2 (en) * 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7093221B2 (en) * 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US7480885B2 (en) * 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US6996789B2 (en) * 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7624367B2 (en) 2002-11-18 2009-11-24 Cadence Design Systems, Inc. Method and system for routing
US7047513B2 (en) * 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7216308B2 (en) * 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US7003752B2 (en) * 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US7010771B2 (en) * 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7506295B1 (en) * 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7096445B1 (en) 2003-01-14 2006-08-22 Cadence Design Systems, Inc. Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit
US7243328B2 (en) * 2003-05-07 2007-07-10 Cadence Design Systems, Inc. Method and apparatus for representing items in a design layout
US7100135B2 (en) * 2004-06-18 2006-08-29 Intel Corporation Method and system to evaluate signal line spacing
US7191425B1 (en) * 2004-11-18 2007-03-13 Sun Microsystems, Inc. Method and apparatus for inserting extra tracks during library architecture migration
JP4817746B2 (ja) * 2005-07-27 2011-11-16 株式会社東芝 半導体装置の設計データ処理方法、そのプログラム、及び半導体装置の製造方法
US20070220472A1 (en) * 2006-02-28 2007-09-20 Inventec Corporation Computer aided wave-shaped circuit line drawing method and system
JP4637043B2 (ja) * 2006-03-23 2011-02-23 新光電気工業株式会社 自動配線整形方法および自動配線整形装置
US8161426B2 (en) * 2009-01-30 2012-04-17 Synopsys, Inc. Method and system for sizing polygons in an integrated circuit (IC) layout
US8146025B2 (en) * 2009-07-30 2012-03-27 United Microelectronics Corp. Method for correcting layout pattern using rule checking rectangle
JP7119688B2 (ja) * 2018-07-18 2022-08-17 株式会社ニューフレアテクノロジー 描画データ生成方法、プログラム、及びマルチ荷電粒子ビーム描画装置
US11106850B2 (en) * 2019-09-04 2021-08-31 International Business Machines Corporation Flexible constraint-based logic cell placement

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097422A (en) * 1986-10-10 1992-03-17 Cascade Design Automation Corporation Method and apparatus for designing integrated circuits
DE3935418A1 (de) * 1988-10-24 1990-04-26 Hitachi Ltd Verfahren und vorrichtung zur bestimmung von verdrahtungsmustern
US5113451A (en) * 1989-10-16 1992-05-12 Vlsi Technology, Inc. Method for labelling polygons
US5416722A (en) * 1992-11-19 1995-05-16 Vlsi Technology, Inc. System and method for compacting integrated circuit layouts
US5581475A (en) * 1993-08-13 1996-12-03 Harris Corporation Method for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules
US5613102A (en) * 1993-11-30 1997-03-18 Lucent Technologies Inc. Method of compressing data for use in performing VLSI mask layout verification
US5515293A (en) * 1993-12-22 1996-05-07 Vlsi Technology, Inc. Method and apparatus for generating a linked data structure for integrated circuit layout
US5625568A (en) * 1993-12-22 1997-04-29 Vlsi Technology, Inc. Method and apparatus for compacting integrated circuits with standard cell architectures
US5524182A (en) * 1994-12-21 1996-06-04 Hewlett-Packard Company System and method for compressing and decompressing fonts based upon font stroke regularities
US5640497A (en) * 1995-01-23 1997-06-17 Woolbright; Phillip Alexander Layout redesign using polygon manipulation

Also Published As

Publication number Publication date
JP3710710B2 (ja) 2005-10-26
IL135870A0 (en) 2001-05-20
CA2308707A1 (en) 1999-05-14
EP1324234A1 (de) 2003-07-02
TW515066B (en) 2002-12-21
KR100399645B1 (ko) 2003-09-29
DE69813892T2 (de) 2004-02-26
EP1324234B1 (de) 2004-06-23
WO1999023699A2 (en) 1999-05-14
DE69824765T2 (de) 2005-07-21
IL135870A (en) 2005-03-20
JP2001522111A (ja) 2001-11-13
EP1044471B1 (de) 2003-04-23
CA2308707C (en) 2005-01-11
US6128767A (en) 2000-10-03
DE69824765D1 (de) 2004-07-29
WO1999023699A3 (en) 1999-07-22
KR20010031616A (ko) 2001-04-16
EP1044471A2 (de) 2000-10-18

Similar Documents

Publication Publication Date Title
DE69813892D1 (de) Polygon darstellung im layout eines integrierten schaltkreises
DE60044328D1 (de) Versorgungs- und masseleitungsführung in einem integrierten schaltkreis
DE69929043D1 (de) Verbesserung bezüglich elektronischer badges
DE69902454D1 (de) Authentifizierte elektronische coupon-ausgabe und -einlösung
DE69839775D1 (de) Kondensatoren in integrierten schaltkreisen
NO20002268L (no) Integrert krets med flaggregister til bruk i seleksjon av permanente celler i volumoperasjoner
DE69712138D1 (de) Integrierte Schaltung mit Feldeffekttransistoren
DE69905364D1 (de) Fräsvorrichtung im bohrloch
FI972187A (fi) Kytkentäjärjestely päätepiirissä
GB2335097B (en) Mixed-signal circuitry and integrated circuit devices
DE69919986D1 (de) Hydrophob modifiziertes polysaccharid in wasserfreien schweisshemmende mitteln
EP1041666A4 (de) Nichtstrahlender dielektrischer wellenleiter und seine integrierte schaltung
DE69836625D1 (de) Prüfen der funktionellen blöcke in einer integrierten halbleiterschaltung
FI991218A0 (fi) Elektroniikkalaitteen laajennuskortin antennirakenne
ITRM20010522A1 (it) Sequenziale di "power-on-reset" condizionato e robusto a potenza ultrabassa per circuiti integrati.
DK1020031T3 (da) Integreret kredsløb
FR2773020B1 (fr) Circuit de distribution d'horloge dans un circuit integre
DE69717066T2 (de) Wiegevorrichtung mit im Wägetisch integrierter Tastatur
DE59912177D1 (de) Kombinierte Vorlade- und Homogenisierschaltung
DE59801698D1 (de) Integrierte vollbrückenschaltung mit vier transistoren
DE29821192U1 (de) Waren-Präsentations- und Darbietungseinrichtung
FR2796497B1 (fr) Interconnexion perfectionnee entre un composant electronique et une carte
FI980005A (fi) Integroitu kertojapiiri
DE10085105D2 (de) Darstellung von Emotionen in elektronischen Geräten
DE29711321U1 (de) Chipkarte mit integriertem Anzeigefeld

Legal Events

Date Code Title Description
8364 No opposition during term of opposition