IL129058A - Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method - Google Patents

Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Info

Publication number
IL129058A
IL129058A IL12905899A IL12905899A IL129058A IL 129058 A IL129058 A IL 129058A IL 12905899 A IL12905899 A IL 12905899A IL 12905899 A IL12905899 A IL 12905899A IL 129058 A IL129058 A IL 129058A
Authority
IL
Israel
Prior art keywords
circuit
practicing
random access
access memory
write operation
Prior art date
Application number
IL12905899A
Other languages
English (en)
Other versions
IL129058A0 (en
Inventor
Ashish Pancholy
Cathal G Phelan
Simon J Lovett
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26760858&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=IL129058(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of IL129058A0 publication Critical patent/IL129058A0/xx
Publication of IL129058A publication Critical patent/IL129058A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
IL12905899A 1998-03-20 1999-03-18 Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method IL129058A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7871898P 1998-03-20 1998-03-20
US09/238,270 US6069839A (en) 1998-03-20 1999-01-27 Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Publications (2)

Publication Number Publication Date
IL129058A0 IL129058A0 (en) 2000-02-17
IL129058A true IL129058A (en) 2005-05-17

Family

ID=26760858

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12905899A IL129058A (en) 1998-03-20 1999-03-18 Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Country Status (3)

Country Link
US (2) US6069839A (xx)
JP (1) JP4869460B2 (xx)
IL (1) IL129058A (xx)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3304577B2 (ja) * 1993-12-24 2002-07-22 三菱電機株式会社 半導体記憶装置とその動作方法
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US6804760B2 (en) 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US6525971B2 (en) 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US7681005B1 (en) * 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US6981126B1 (en) * 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US6262937B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
US6262936B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Random access memory having independent read port and write port and process for writing to and reading from the same
US6069839A (en) * 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
JP4569915B2 (ja) * 2000-08-11 2010-10-27 エルピーダメモリ株式会社 半導体記憶装置
US7006634B1 (en) * 2000-09-28 2006-02-28 Cisco Technology, Inc. Hardware-based encryption/decryption employing dual ported key storage
US6873707B1 (en) * 2000-09-28 2005-03-29 Cisco Technology, Inc. Hardware-based encryption/decryption employing cycle stealing
US7128266B2 (en) * 2003-11-13 2006-10-31 Metrologic Instruments. Inc. Hand-supportable digital imaging-based bar code symbol reader supporting narrow-area and wide-area modes of illumination and image capture
US6788593B2 (en) * 2001-02-28 2004-09-07 Rambus, Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
KR100415192B1 (ko) * 2001-04-18 2004-01-16 삼성전자주식회사 반도체 메모리 장치에서 읽기와 쓰기 방법 및 장치
ITMI20021185A1 (it) * 2002-05-31 2003-12-01 St Microelectronics Srl Dispositivo e metodo di lettura per memorie non volatili dotate di almeno un'interfaccia di comunicazione pseudo parallela
US6750497B2 (en) * 2002-08-22 2004-06-15 Micron Technology, Inc. High-speed transparent refresh DRAM-based memory cell
DE10244401B4 (de) * 2002-09-24 2018-02-08 Polaris Innovations Ltd. Bauelement mit Takt-Weiterleitungs-Einrichtung
US6876595B2 (en) * 2003-06-05 2005-04-05 International Business Machines Corporation Decode path gated low active power SRAM
US7535772B1 (en) 2003-06-27 2009-05-19 Cypress Semiconductor Corporation Configurable data path architecture and clocking scheme
US7142479B2 (en) * 2004-04-19 2006-11-28 Nokia Corporation Addressing data within dynamic random access memory
US7132854B1 (en) 2004-09-23 2006-11-07 Cypress Semiconductor Corporation Data path configurable for multiple clocking arrangements
US7484061B1 (en) * 2005-04-06 2009-01-27 Sun Microsystems, Inc. Method for performing swap operation and apparatus for implementing the same
US7873953B1 (en) * 2006-01-20 2011-01-18 Altera Corporation High-level language code sequence optimization for implementing programmable chip designs
US7538592B2 (en) * 2006-11-15 2009-05-26 Spi Electronic Co., Ltd. Pulse controller with dual latches
US8149643B2 (en) 2008-10-23 2012-04-03 Cypress Semiconductor Corporation Memory device and method
KR101586844B1 (ko) 2010-01-06 2016-02-02 삼성전자주식회사 영상 처리 장치 및 방법
US9378789B2 (en) 2014-09-26 2016-06-28 Qualcomm Incorporated Voltage level shifted self-clocked write assistance
US9653152B1 (en) * 2016-11-15 2017-05-16 Qualcomm Incorporated Low voltage high sigma multi-port memory control

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4169284A (en) 1978-03-07 1979-09-25 International Business Machines Corporation Cache control for concurrent access
US4245304A (en) 1978-12-11 1981-01-13 Honeywell Information Systems Inc. Cache arrangement utilizing a split cycle mode of operation
US4456965A (en) 1980-10-14 1984-06-26 Texas Instruments Incorporated Data processing system having multiple buses
US4539661A (en) 1982-06-30 1985-09-03 Fujitsu Limited Static-type semiconductor memory device
US4599708A (en) 1983-12-30 1986-07-08 International Business Machines Corporation Method and structure for machine data storage with simultaneous write and read
US4575826A (en) * 1984-02-27 1986-03-11 International Business Machines Corp. Refresh generator system for a dynamic memory
DE3543911A1 (de) 1984-12-14 1986-06-26 Mitsubishi Denki K.K., Tokio/Tokyo Digitale verzoegerungseinheit
JPS6297036A (ja) 1985-07-31 1987-05-06 テキサス　インスツルメンツ　インコ−ポレイテツド 計算機システム
US4783732A (en) 1985-12-12 1988-11-08 Itt Corporation Two-wire/three-port RAM for cellular array processor
JPS63202045A (ja) * 1987-02-17 1988-08-22 Matsushita Electronics Corp 半導体装置
US5983328A (en) 1987-03-13 1999-11-09 Texas Instruments Incorporated Data processing device with time-multiplexed memory bus
JPS6443894A (en) * 1987-08-10 1989-02-16 Nec Corp Semiconductor memory
JPH077901B2 (ja) * 1988-02-29 1995-01-30 沖電気工業株式会社 フリップフロップ回路
US4882709A (en) 1988-08-25 1989-11-21 Integrated Device Technology, Inc. Conditional write RAM
US5023838A (en) 1988-12-02 1991-06-11 Ncr Corporation Random access memory device with integral logic capability
US5598545A (en) 1989-10-13 1997-01-28 Texas Instruments Incorporated Circuitry and method for performing two operating instructions during a single clock in a processing device
JPH0581864A (ja) * 1991-09-25 1993-04-02 Nec Corp 記憶装置
US5394361A (en) 1992-10-22 1995-02-28 At&T Corp. Read/write memory
US5309395A (en) 1992-10-22 1994-05-03 At&T Bell Laboratories Synchronous static random access memory
US5546569A (en) 1993-02-19 1996-08-13 Intergraph Corporation Apparatus for writing data to and reading data from a multi-port RAM in a single clock cycle
KR970008188B1 (ko) * 1993-04-08 1997-05-21 가부시끼가이샤 히다찌세이사꾸쇼 플래시메모리의 제어방법 및 그것을 사용한 정보처리장치
JPH0756815A (ja) 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ
JP3304577B2 (ja) 1993-12-24 2002-07-22 三菱電機株式会社 半導体記憶装置とその動作方法
JPH07221605A (ja) * 1994-02-08 1995-08-18 Hitachi Ltd ラッチ回路並びにそれを用いたレジスタ回路およびパイプライン処理回路
US5648987A (en) * 1994-03-24 1997-07-15 Samsung Electronics Co., Ltd. Rapid-update adaptive channel-equalization filtering for digital radio receivers, such as HDTV receivers
US5638534A (en) 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
JPH09320269A (ja) * 1996-05-31 1997-12-12 Nippon Steel Corp アドレス装置
KR100227272B1 (ko) 1996-08-08 1999-11-01 윤종용 1 사이클 동작 내부 리드/라이트 기능을 가진 반도체 메모리 장치
KR100252056B1 (ko) * 1997-12-27 2000-05-01 윤종용 반도체 메모리의 어드레스 디코우딩 장치
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6069839A (en) * 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
JP4159657B2 (ja) * 1998-07-13 2008-10-01 株式会社ルネサステクノロジ 同期型半導体記憶装置

Also Published As

Publication number Publication date
IL129058A0 (en) 2000-02-17
JPH11328976A (ja) 1999-11-30
US6069839A (en) 2000-05-30
US6292403B1 (en) 2001-09-18
JP4869460B2 (ja) 2012-02-08

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Legal Events

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MM9K Patent not in force due to non-payment of renewal fees