IL122260A - Interface circuit between asynchronously operating buses - Google Patents

Interface circuit between asynchronously operating buses

Info

Publication number
IL122260A
IL122260A IL12226096A IL12226096A IL122260A IL 122260 A IL122260 A IL 122260A IL 12226096 A IL12226096 A IL 12226096A IL 12226096 A IL12226096 A IL 12226096A IL 122260 A IL122260 A IL 122260A
Authority
IL
Israel
Prior art keywords
interface circuit
asynchronously operating
operating buses
buses
asynchronously
Prior art date
Application number
IL12226096A
Other languages
English (en)
Other versions
IL122260A0 (en
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of IL122260A0 publication Critical patent/IL122260A0/xx
Publication of IL122260A publication Critical patent/IL122260A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)
IL12226096A 1995-06-07 1996-06-06 Interface circuit between asynchronously operating buses IL122260A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US48350595A 1995-06-07 1995-06-07
US51054595A 1995-08-02 1995-08-02
PCT/US1996/008573 WO1996041267A1 (en) 1995-06-07 1996-06-06 Delay reduction in transfer of buffered data between two mutually asynchronous buses

Publications (2)

Publication Number Publication Date
IL122260A0 IL122260A0 (en) 1998-04-05
IL122260A true IL122260A (en) 2001-01-11

Family

ID=27047672

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12226096A IL122260A (en) 1995-06-07 1996-06-06 Interface circuit between asynchronously operating buses

Country Status (11)

Country Link
US (1) US5764966A (de)
EP (1) EP0834134B1 (de)
JP (2) JP3873089B2 (de)
KR (1) KR100258986B1 (de)
CN (1) CN1093963C (de)
AU (1) AU6035296A (de)
DE (1) DE69634358T2 (de)
IL (1) IL122260A (de)
RU (1) RU2176814C2 (de)
TW (1) TW303438B (de)
WO (2) WO1996041268A1 (de)

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US5898889A (en) * 1996-04-30 1999-04-27 3Com Corporation Qualified burst cache for transfer of data between disparate clock domains
US6119190A (en) * 1996-11-06 2000-09-12 Intel Corporation Method to reduce system bus load due to USB bandwidth reclamation
JPH10269775A (ja) 1997-03-27 1998-10-09 Mitsubishi Electric Corp 半導体集積回路および位相同期ループ回路
AU9798698A (en) 1997-10-10 1999-05-03 Rambus Incorporated Method and apparatus for fail-safe resynchronization with minimum latency
US6055597A (en) * 1997-10-30 2000-04-25 Micron Electronics, Inc. Bi-directional synchronizing buffer system
US6076160A (en) * 1997-11-20 2000-06-13 Advanced Micro Devices, Inc. Hardware-based system for enabling data transfers between a CPU and chip set logic of a computer system on both edges of bus clock signal
US6279065B1 (en) * 1998-06-03 2001-08-21 Compaq Computer Corporation Computer system with improved memory access
US6366989B1 (en) * 1998-09-17 2002-04-02 Sun Microsystems, Inc. Programmable memory controller
ES2267303T3 (es) * 1998-10-30 2007-03-01 Avocent Huntsville Corporation Ordenador dividido.
US6418494B1 (en) 1998-10-30 2002-07-09 Cybex Computer Products Corporation Split computer architecture to separate user and processor while retaining original user interface
US6560652B1 (en) * 1998-11-20 2003-05-06 Legerity, Inc. Method and apparatus for accessing variable sized blocks of data
WO2001035234A1 (en) * 1999-11-05 2001-05-17 Analog Devices, Inc. Generic serial port architecture and system
EP1150467A1 (de) * 2000-04-28 2001-10-31 STMicroelectronics S.r.l. Kodierstruktur für Parellelbusse
US6782486B1 (en) * 2000-08-11 2004-08-24 Advanced Micro Devices, Inc. Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer
JP2003157228A (ja) * 2001-11-20 2003-05-30 Fujitsu Ltd データ転送回路
GB0204144D0 (en) * 2002-02-22 2002-04-10 Koninkl Philips Electronics Nv Transferring data between differently clocked busses
US7321623B2 (en) 2002-10-01 2008-01-22 Avocent Corporation Video compression system
US20040111563A1 (en) * 2002-12-10 2004-06-10 Edirisooriya Samantha J. Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors
CN100370415C (zh) * 2003-04-26 2008-02-20 华为技术有限公司 基于fifo队列的数据包线速处理方法及其装置
CN1323529C (zh) * 2003-04-28 2007-06-27 华为技术有限公司 一种数字信号处理器内部数据传输的方法
US7269783B2 (en) 2003-04-30 2007-09-11 Lucent Technologies Inc. Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching
US9560371B2 (en) * 2003-07-30 2017-01-31 Avocent Corporation Video compression system
KR100546403B1 (ko) * 2004-02-19 2006-01-26 삼성전자주식회사 감소된 메모리 버스 점유 시간을 가지는 시리얼 플레쉬메모리 컨트롤러
US7457461B2 (en) * 2004-06-25 2008-11-25 Avocent Corporation Video compression noise immunity
JP2006113689A (ja) * 2004-10-12 2006-04-27 Fujitsu Ltd バスブリッジ装置およびデータ転送方法
KR101160566B1 (ko) * 2004-11-25 2012-06-28 텔레콤 이탈리아 소시에떼 퍼 아찌오니 이동 통신장비용 결합 ｉｃ 카드 및 무선 트랜시버 모듈
JP4786262B2 (ja) * 2005-09-06 2011-10-05 ルネサスエレクトロニクス株式会社 インターフェイス回路
TWI310501B (en) * 2005-10-06 2009-06-01 Via Tech Inc Bus controller and data buffer allocation method
US7519754B2 (en) * 2005-12-28 2009-04-14 Silicon Storage Technology, Inc. Hard disk drive cache memory and playback device
US20070147115A1 (en) * 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
US7783820B2 (en) * 2005-12-30 2010-08-24 Avocent Corporation Packet-switched split computer having disassociated peripheral controller and plural data buses
US7793021B2 (en) 2006-01-05 2010-09-07 Freescale Semiconductor, Inc. Method for synchronizing a transmission of information and a device having synchronizing capabilities
TW200814780A (en) * 2006-04-28 2008-03-16 Avocent Corp DVC delta commands
CN100405343C (zh) * 2006-06-21 2008-07-23 北京中星微电子有限公司 一种异步数据缓存装置
JP4692632B2 (ja) 2006-07-25 2011-06-01 株式会社ニコン 画像処理方法、画像処理プログラム、および画像処理装置
WO2009069094A1 (en) * 2007-11-30 2009-06-04 Nxp B.V. Method and device for routing data between components
US8363766B2 (en) * 2008-06-06 2013-01-29 Freescale Semiconductor, Inc. Device and method of synchronizing signals
CN101944075B (zh) * 2010-07-21 2012-06-27 北京星网锐捷网络技术有限公司 总线系统、对低速总线设备进行读写操作的方法及装置
CN103440219B (zh) * 2013-08-23 2016-06-08 上海航天测控通信研究所 一种通用总线转换桥ip核
US9910818B2 (en) * 2013-10-02 2018-03-06 Lattice Semiconductor Corporation Serdes interface architecture for multi-processor systems
US20160173134A1 (en) * 2014-12-15 2016-06-16 Intel Corporation Enhanced Data Bus Invert Encoding for OR Chained Buses

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Publication number Priority date Publication date Assignee Title
JPS63255760A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp 制御システム
US5117486A (en) * 1989-04-21 1992-05-26 International Business Machines Corp. Buffer for packetizing block of data with different sizes and rates received from first processor before transferring to second processor
EP0433520B1 (de) * 1989-12-22 1996-02-14 International Business Machines Corporation Elastischer konfigurierbarer Pufferspeicher zum Puffern von asynchronen Daten
US5274763A (en) * 1990-12-28 1993-12-28 Apple Computer, Inc. Data path apparatus for IO adapter
US5535341A (en) * 1994-02-24 1996-07-09 Intel Corporation Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation

Also Published As

Publication number Publication date
IL122260A0 (en) 1998-04-05
JP4237769B2 (ja) 2009-03-11
CN1093963C (zh) 2002-11-06
US5764966A (en) 1998-06-09
JPH11506851A (ja) 1999-06-15
TW303438B (de) 1997-04-21
WO1996041267A1 (en) 1996-12-19
DE69634358T2 (de) 2005-12-29
RU2176814C2 (ru) 2001-12-10
CN1192282A (zh) 1998-09-02
JP2006202313A (ja) 2006-08-03
AU6035296A (en) 1996-12-30
DE69634358D1 (de) 2005-03-24
EP0834134B1 (de) 2005-02-16
WO1996041268A1 (en) 1996-12-19
EP0834134A1 (de) 1998-04-08
EP0834134A4 (de) 2002-05-08
JP3873089B2 (ja) 2007-01-24
KR19990022339A (ko) 1999-03-25
KR100258986B1 (ko) 2000-06-15

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