IE51323B1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device

Info

Publication number
IE51323B1
IE51323B1 IE936/81A IE93681A IE51323B1 IE 51323 B1 IE51323 B1 IE 51323B1 IE 936/81 A IE936/81 A IE 936/81A IE 93681 A IE93681 A IE 93681A IE 51323 B1 IE51323 B1 IE 51323B1
Authority
IE
Ireland
Prior art keywords
region
layer
buried
conductivity type
epitaxial layer
Prior art date
Application number
IE936/81A
Other languages
English (en)
Other versions
IE810936L (en
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of IE810936L publication Critical patent/IE810936L/xx
Publication of IE51323B1 publication Critical patent/IE51323B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/125Shapes of junctions between the regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/859Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
IE936/81A 1980-04-29 1981-04-27 Method of manufacturing a semiconductor device IE51323B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NLAANVRAGE8002492,A NL186662C (nl) 1980-04-29 1980-04-29 Werkwijze ter vervaardiging van een halfgeleiderinrichting.

Publications (2)

Publication Number Publication Date
IE810936L IE810936L (en) 1981-10-29
IE51323B1 true IE51323B1 (en) 1986-12-10

Family

ID=19835227

Family Applications (1)

Application Number Title Priority Date Filing Date
IE936/81A IE51323B1 (en) 1980-04-29 1981-04-27 Method of manufacturing a semiconductor device

Country Status (11)

Country Link
US (1) US4466171A (enExample)
JP (1) JPS571260A (enExample)
AU (1) AU544817B2 (enExample)
CA (1) CA1165012A (enExample)
CH (1) CH655202A5 (enExample)
DE (1) DE3116268C2 (enExample)
FR (1) FR2481518A1 (enExample)
GB (1) GB2075257B (enExample)
IE (1) IE51323B1 (enExample)
IT (1) IT1137566B (enExample)
NL (1) NL186662C (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8104862A (nl) * 1981-10-28 1983-05-16 Philips Nv Halfgeleiderinrichting, en werkwijze ter vervaardiging daarvan.
DE3149185A1 (de) * 1981-12-11 1983-06-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
NL188923C (nl) * 1983-07-05 1992-11-02 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4683488A (en) * 1984-03-29 1987-07-28 Hughes Aircraft Company Latch-up resistant CMOS structure for VLSI including retrograded wells
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4727044A (en) 1984-05-18 1988-02-23 Semiconductor Energy Laboratory Co., Ltd. Method of making a thin film transistor with laser recrystallized source and drain
US4677739A (en) * 1984-11-29 1987-07-07 Texas Instruments Incorporated High density CMOS integrated circuit manufacturing process
US4578128A (en) * 1984-12-03 1986-03-25 Ncr Corporation Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants
JPH0648716B2 (ja) * 1985-11-30 1994-06-22 ヤマハ株式会社 集積回路装置の製法
DE3765844D1 (de) * 1986-06-10 1990-12-06 Siemens Ag Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen.
US4743563A (en) * 1987-05-26 1988-05-10 Motorola, Inc. Process of controlling surface doping
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
JPH01161752A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 半導体装置製造方法
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
US5181094A (en) * 1988-09-29 1993-01-19 Mitsubishi Denki Kabushiki Kaisha Complementary semiconductor device having improved device isolating region
US5454258A (en) * 1994-05-09 1995-10-03 Olin Corporation Broad range moisture analyzer and method
US5556796A (en) * 1995-04-25 1996-09-17 Micrel, Inc. Self-alignment technique for forming junction isolation and wells
JP4677166B2 (ja) * 2002-06-27 2011-04-27 三洋電機株式会社 半導体装置及びその製造方法
WO2005103172A2 (en) * 2004-04-15 2005-11-03 Avery Dennison Corporation Dew resistant coatings

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3928091A (en) * 1971-09-27 1975-12-23 Hitachi Ltd Method for manufacturing a semiconductor device utilizing selective oxidation
US3865654A (en) * 1972-11-01 1975-02-11 Ibm Complementary field effect transistor having p doped silicon gates and process for making the same
US3793088A (en) * 1972-11-15 1974-02-19 Bell Telephone Labor Inc Compatible pnp and npn devices in an integrated circuit
US4099998A (en) * 1975-11-03 1978-07-11 General Electric Company Method of making zener diodes with selectively variable breakdown voltages
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
JPS5370679A (en) * 1976-12-06 1978-06-23 Nippon Gakki Seizo Kk Transistor
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
US4151010A (en) * 1978-06-30 1979-04-24 International Business Machines Corporation Forming adjacent impurity regions in a semiconductor by oxide masking
US4168997A (en) * 1978-10-10 1979-09-25 National Semiconductor Corporation Method for making integrated circuit transistors with isolation and substrate connected collectors utilizing simultaneous outdiffusion to convert an epitaxial layer
US4373253A (en) * 1981-04-13 1983-02-15 National Semiconductor Corporation Integrated CMOS process with JFET

Also Published As

Publication number Publication date
AU6987581A (en) 1981-11-05
DE3116268A1 (de) 1982-05-19
GB2075257B (en) 1984-06-06
JPS571260A (en) 1982-01-06
FR2481518A1 (fr) 1981-10-30
NL186662C (nl) 1992-03-16
IT8121369A0 (it) 1981-04-24
NL8002492A (nl) 1981-12-01
CH655202A5 (de) 1986-03-27
IT1137566B (it) 1986-09-10
NL186662B (nl) 1990-08-16
AU544817B2 (en) 1985-06-13
IT8121369A1 (it) 1982-10-24
FR2481518B1 (enExample) 1984-11-09
CA1165012A (en) 1984-04-03
IE810936L (en) 1981-10-29
US4466171A (en) 1984-08-21
DE3116268C2 (de) 1986-03-20
GB2075257A (en) 1981-11-11

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