HK1177523A1 - 用於存儲器裝置的可變阻抗控制 - Google Patents

用於存儲器裝置的可變阻抗控制

Info

Publication number
HK1177523A1
HK1177523A1 HK13104396.7A HK13104396A HK1177523A1 HK 1177523 A1 HK1177523 A1 HK 1177523A1 HK 13104396 A HK13104396 A HK 13104396A HK 1177523 A1 HK1177523 A1 HK 1177523A1
Authority
HK
Hong Kong
Prior art keywords
memory devices
variable impedance
impedance control
variable
control
Prior art date
Application number
HK13104396.7A
Other languages
English (en)
Inventor
Anthony Fai
Nicholas Seroff
Original Assignee
Apple Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc filed Critical Apple Inc
Publication of HK1177523A1 publication Critical patent/HK1177523A1/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Networks Using Active Elements (AREA)
  • Semiconductor Memories (AREA)
HK13104396.7A 2011-02-22 2013-04-10 用於存儲器裝置的可變阻抗控制 HK1177523A1 (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/032,560 US8681546B2 (en) 2011-02-22 2011-02-22 Variable impedance control for memory devices

Publications (1)

Publication Number Publication Date
HK1177523A1 true HK1177523A1 (zh) 2013-08-23

Family

ID=45656569

Family Applications (1)

Application Number Title Priority Date Filing Date
HK13104396.7A HK1177523A1 (zh) 2011-02-22 2013-04-10 用於存儲器裝置的可變阻抗控制

Country Status (7)

Country Link
US (1) US8681546B2 (zh)
EP (1) EP2521040B1 (zh)
JP (1) JP2012174281A (zh)
KR (2) KR101320731B1 (zh)
HK (1) HK1177523A1 (zh)
TW (2) TWI498914B (zh)
WO (1) WO2012115975A1 (zh)

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US9444455B2 (en) * 2013-12-10 2016-09-13 Sandisk Technologies Llc Load impedance adjustment for an interface of a data storage device
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US10565151B2 (en) * 2017-11-09 2020-02-18 Micron Technology, Inc. Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same
KR102442620B1 (ko) 2018-01-02 2022-09-13 삼성전자 주식회사 반도체 메모리 패키지
US11217284B2 (en) * 2020-04-03 2022-01-04 Micron Technology, Inc. Memory with per pin input/output termination and driver impedance calibration
KR20220112322A (ko) * 2021-02-03 2022-08-11 삼성전자주식회사 송신 회로의 출력 임피던스를 조절할 수 있는 인터페이스 회로 및 이를 포함하는 이미지 센서
US20230030168A1 (en) * 2021-07-27 2023-02-02 Dell Products L.P. Protection of i/o paths against network partitioning and component failures in nvme-of environments

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Also Published As

Publication number Publication date
EP2521040A2 (en) 2012-11-07
KR20120096443A (ko) 2012-08-30
TWI498914B (zh) 2015-09-01
EP2521040A3 (en) 2013-01-16
TWI512752B (zh) 2015-12-11
TW201248642A (en) 2012-12-01
US8681546B2 (en) 2014-03-25
KR101320731B1 (ko) 2013-10-21
TW201303883A (zh) 2013-01-16
US20120215958A1 (en) 2012-08-23
JP2012174281A (ja) 2012-09-10
WO2012115975A1 (en) 2012-08-30
KR20120096440A (ko) 2012-08-30
EP2521040B1 (en) 2014-06-04

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20230221