HK1161355A1 - A method of and an arrangement for testing connections on a printed circuit board - Google Patents

A method of and an arrangement for testing connections on a printed circuit board

Info

Publication number
HK1161355A1
HK1161355A1 HK12101567.7A HK12101567A HK1161355A1 HK 1161355 A1 HK1161355 A1 HK 1161355A1 HK 12101567 A HK12101567 A HK 12101567A HK 1161355 A1 HK1161355 A1 HK 1161355A1
Authority
HK
Hong Kong
Prior art keywords
arrangement
circuit board
printed circuit
testing connections
connections
Prior art date
Application number
HK12101567.7A
Other languages
English (en)
Chinese (zh)
Inventor
彼得勒斯‧馬里納斯‧科內利森‧馬麗亞‧瓦‧登‧艾杰登
Original Assignee
技術有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 技術有限公司 filed Critical 技術有限公司
Publication of HK1161355A1 publication Critical patent/HK1161355A1/xx

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
HK12101567.7A 2009-11-10 2012-02-17 A method of and an arrangement for testing connections on a printed circuit board HK1161355A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25977209P 2009-11-10 2009-11-10
NL1037457A NL1037457C2 (en) 2009-11-10 2009-11-10 A method of and an arrangement for testing connections on a printed circuit board.

Publications (1)

Publication Number Publication Date
HK1161355A1 true HK1161355A1 (en) 2012-08-24

Family

ID=42227625

Family Applications (1)

Application Number Title Priority Date Filing Date
HK12101567.7A HK1161355A1 (en) 2009-11-10 2012-02-17 A method of and an arrangement for testing connections on a printed circuit board

Country Status (6)

Country Link
US (1) US8601333B2 (ja)
EP (1) EP2320241B1 (ja)
JP (1) JP5688270B2 (ja)
CN (1) CN102156255B (ja)
HK (1) HK1161355A1 (ja)
NL (1) NL1037457C2 (ja)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL2006759C2 (en) 2011-05-10 2012-11-13 Jtag Technologies Bv A method of and an arrangement for automatically measuring electric connections of electronic circuit arrangements mounted on printed circuit boards.
US9064074B2 (en) * 2011-11-14 2015-06-23 International Business Machines Corporation Retrieving odd net topology in hierarchical circuit designs
US9548438B2 (en) 2014-03-31 2017-01-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Acoustic resonator comprising acoustic redistribution layers
CN103941175A (zh) * 2014-04-01 2014-07-23 无锡市同翔科技有限公司 一种边界扫描测试系统及方法
JP6496562B2 (ja) * 2014-04-11 2019-04-03 ルネサスエレクトロニクス株式会社 半導体装置、診断テスト方法及び診断テスト回路
CN104198921B (zh) * 2014-09-24 2017-01-25 四川泰鹏测控仪表科技有限公司 一种印刷电路板的测试方法
CN107402346A (zh) * 2016-05-20 2017-11-28 致伸科技股份有限公司 电路板测试系统
CN110389291B (zh) * 2018-04-17 2020-11-20 大唐移动通信设备有限公司 一种集成电路印制板的测试装置及测试方法
US10866283B2 (en) * 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester
CN111367727B (zh) * 2018-12-25 2023-11-17 中兴通讯股份有限公司 连接器结构，时延差的计算方法及装置
US11293979B2 (en) * 2019-10-22 2022-04-05 Peter Shun Shen Wang Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die
NL2024200B1 (en) * 2019-11-08 2021-07-20 Jtag Tech B V A method for debugging a printed circuit board.
EP4070315A4 (en) 2019-12-04 2023-11-29 Proteantecs Ltd. MONITORING DEGRADATION OF A STORAGE DEVICE
JP2021135178A (ja) * 2020-02-27 2021-09-13 セイコーエプソン株式会社 半導体装置
US11815551B1 (en) * 2022-06-07 2023-11-14 Proteantecs Ltd. Die-to-die connectivity monitoring using a clocked receiver

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Also Published As

Publication number Publication date
US20110113298A1 (en) 2011-05-12
JP2011102803A (ja) 2011-05-26
US8601333B2 (en) 2013-12-03
NL1037457C2 (en) 2011-05-12
CN102156255B (zh) 2015-02-25
CN102156255A (zh) 2011-08-17
JP5688270B2 (ja) 2015-03-25
EP2320241A1 (en) 2011-05-11
EP2320241B1 (en) 2013-01-09

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