HK1058283A1 - Parallel plane substrate - Google Patents

Parallel plane substrate

Info

Publication number
HK1058283A1
HK1058283A1 HK04100905A HK04100905A HK1058283A1 HK 1058283 A1 HK1058283 A1 HK 1058283A1 HK 04100905 A HK04100905 A HK 04100905A HK 04100905 A HK04100905 A HK 04100905A HK 1058283 A1 HK1058283 A1 HK 1058283A1
Authority
HK
Hong Kong
Prior art keywords
parallel plane
plane substrate
conductive material
dielectric material
layers
Prior art date
Application number
HK04100905A
Other languages
English (en)
Inventor
Sankman Robert
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1058283A1 publication Critical patent/HK1058283A1/xx

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/1028Thin metal strips as connectors or conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0235Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Bipolar Transistors (AREA)
  • Inorganic Insulating Materials (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Recrystallisation Techniques (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
HK04100905A 2000-12-19 2004-02-11 Parallel plane substrate HK1058283A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/741,206 US6563210B2 (en) 2000-12-19 2000-12-19 Parallel plane substrate
PCT/US2001/044788 WO2002051222A2 (en) 2000-12-19 2001-11-15 Parallel plane substrate

Publications (1)

Publication Number Publication Date
HK1058283A1 true HK1058283A1 (en) 2004-05-07

Family

ID=24979788

Family Applications (1)

Application Number Title Priority Date Filing Date
HK04100905A HK1058283A1 (en) 2000-12-19 2004-02-11 Parallel plane substrate

Country Status (11)

Country Link
US (2) US6563210B2 (xx)
EP (1) EP1344435B1 (xx)
JP (1) JP2004527898A (xx)
KR (1) KR100550298B1 (xx)
CN (1) CN1543757A (xx)
AT (1) ATE395807T1 (xx)
AU (1) AU2002228674A1 (xx)
DE (1) DE60134042D1 (xx)
HK (1) HK1058283A1 (xx)
MY (1) MY123629A (xx)
WO (1) WO2002051222A2 (xx)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW566796U (en) * 2003-03-12 2003-12-11 Unimicron Technology Corp Standard printed circuit board core
US7566960B1 (en) * 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
DE102004050476B3 (de) * 2004-10-16 2006-04-06 Infineon Technologies Ag Verfahren zum Herstellen einer Umverdrahtungs-Leiterplatte
WO2007004658A1 (ja) * 2005-06-30 2007-01-11 Ibiden Co., Ltd. プリント配線板
CN101868120A (zh) * 2005-06-30 2010-10-20 揖斐电株式会社 印刷线路板及其制造方法
TWI382502B (zh) * 2007-12-02 2013-01-11 Univ Lunghwa Sci & Technology 晶片封裝之結構改良
JP5257518B2 (ja) * 2009-08-28 2013-08-07 株式会社村田製作所 基板製造方法および樹脂基板
US8963013B2 (en) 2010-12-07 2015-02-24 Masud Beroz Three dimensional interposer device
FR2976720A1 (fr) 2011-06-15 2012-12-21 St Microelectronics Sa Procede de connexion electrique entre des elements d'une structure integree tridimensionnelle, et dispositif correspondant
US20130319759A1 (en) * 2012-05-31 2013-12-05 General Electric Company Fine-pitch flexible wiring
US10003149B2 (en) 2014-10-25 2018-06-19 ComponentZee, LLC Fluid pressure activated electrical contact devices and methods
US10025047B1 (en) 2017-04-14 2018-07-17 Google Llc Integration of silicon photonics IC for high data rate

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1765083A1 (de) 1968-03-29 1971-07-01 Siemens Ag Verfahren zum Herstellen von Traegern zum Aufnehmen und Verbinden elektrischer Bauelemente
DE1930642A1 (de) 1969-06-18 1971-01-07 Siemens Ag Leiterplatte zum Aufnehmen und Verbinden elektrischer Bauelemente
JPS5987893A (ja) 1982-11-12 1984-05-21 株式会社日立製作所 配線基板とその製造方法およびそれを用いた半導体装置
DE3709770A1 (de) 1987-03-25 1988-10-13 Ant Nachrichtentech Leiterplatte, -folie, multilayerinnenlage oder leitersubstrat mit durchkontaktierungen und herstellungsverfahren
JPH01124296A (ja) 1987-11-09 1989-05-17 Hitachi Chem Co Ltd 配線板の製造法
US5363275A (en) * 1993-02-10 1994-11-08 International Business Machines Corporation Modular component computer system
US6353540B1 (en) * 1995-01-10 2002-03-05 Hitachi, Ltd. Low-EMI electronic apparatus, low-EMI circuit board, and method of manufacturing the low-EMI circuit board.
JPH10270809A (ja) 1997-03-28 1998-10-09 Hoya Corp 配線基板およびその製造方法
US6075427A (en) * 1998-01-23 2000-06-13 Lucent Technologies Inc. MCM with high Q overlapping resonator
JPH11233917A (ja) 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc 積層基板の製造方法
US6379781B1 (en) 1998-05-06 2002-04-30 Ngk Insulators, Ltd. Printed circuit board material and method of manufacturing board material and intermediate block body for board material
US6165892A (en) * 1998-07-31 2000-12-26 Kulicke & Soffa Holdings, Inc. Method of planarizing thin film layers deposited over a common circuit base

Also Published As

Publication number Publication date
MY123629A (en) 2006-05-31
JP2004527898A (ja) 2004-09-09
US6563210B2 (en) 2003-05-13
EP1344435B1 (en) 2008-05-14
WO2002051222A3 (en) 2003-02-06
KR100550298B1 (ko) 2006-02-08
ATE395807T1 (de) 2008-05-15
KR20030064423A (ko) 2003-07-31
US20030127742A1 (en) 2003-07-10
WO2002051222A2 (en) 2002-06-27
US6632734B2 (en) 2003-10-14
AU2002228674A1 (en) 2002-07-01
CN1543757A (zh) 2004-11-03
EP1344435A2 (en) 2003-09-17
DE60134042D1 (de) 2008-06-26
US20020074644A1 (en) 2002-06-20

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20131115