DE60134042D1 - Parallelebenensubstrat - Google Patents

Parallelebenensubstrat

Info

Publication number
DE60134042D1
DE60134042D1 DE60134042T DE60134042T DE60134042D1 DE 60134042 D1 DE60134042 D1 DE 60134042D1 DE 60134042 T DE60134042 T DE 60134042T DE 60134042 T DE60134042 T DE 60134042T DE 60134042 D1 DE60134042 D1 DE 60134042D1
Authority
DE
Germany
Prior art keywords
layer substrate
parallel layer
conductive material
dielectric material
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60134042T
Other languages
English (en)
Inventor
Robert Sankman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60134042D1 publication Critical patent/DE60134042D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1028—Thin metal strips as connectors or conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0235—Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Bipolar Transistors (AREA)
  • Inorganic Insulating Materials (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Recrystallisation Techniques (AREA)
DE60134042T 2000-12-19 2001-11-15 Parallelebenensubstrat Expired - Lifetime DE60134042D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/741,206 US6563210B2 (en) 2000-12-19 2000-12-19 Parallel plane substrate
PCT/US2001/044788 WO2002051222A2 (en) 2000-12-19 2001-11-15 Parallel plane substrate

Publications (1)

Publication Number Publication Date
DE60134042D1 true DE60134042D1 (de) 2008-06-26

Family

ID=24979788

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60134042T Expired - Lifetime DE60134042D1 (de) 2000-12-19 2001-11-15 Parallelebenensubstrat

Country Status (11)

Country Link
US (2) US6563210B2 (de)
EP (1) EP1344435B1 (de)
JP (1) JP2004527898A (de)
KR (1) KR100550298B1 (de)
CN (1) CN1543757A (de)
AT (1) ATE395807T1 (de)
AU (1) AU2002228674A1 (de)
DE (1) DE60134042D1 (de)
HK (1) HK1058283A1 (de)
MY (1) MY123629A (de)
WO (1) WO2002051222A2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW566796U (en) * 2003-03-12 2003-12-11 Unimicron Technology Corp Standard printed circuit board core
US7566960B1 (en) 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
DE102004050476B3 (de) * 2004-10-16 2006-04-06 Infineon Technologies Ag Verfahren zum Herstellen einer Umverdrahtungs-Leiterplatte
CN101171895B (zh) * 2005-06-30 2010-06-23 揖斐电株式会社 印刷线路板
EP1887845A4 (de) * 2005-06-30 2010-08-11 Ibiden Co Ltd Leiterplatte
TWI382502B (zh) * 2007-12-02 2013-01-11 Univ Lunghwa Sci & Technology 晶片封裝之結構改良
WO2011024469A1 (ja) * 2009-08-28 2011-03-03 株式会社村田製作所 基板製造方法および樹脂基板
US8963013B2 (en) 2010-12-07 2015-02-24 Masud Beroz Three dimensional interposer device
FR2976720A1 (fr) * 2011-06-15 2012-12-21 St Microelectronics Sa Procede de connexion electrique entre des elements d'une structure integree tridimensionnelle, et dispositif correspondant
US20130319759A1 (en) * 2012-05-31 2013-12-05 General Electric Company Fine-pitch flexible wiring
US10003149B2 (en) 2014-10-25 2018-06-19 ComponentZee, LLC Fluid pressure activated electrical contact devices and methods
US10025047B1 (en) 2017-04-14 2018-07-17 Google Llc Integration of silicon photonics IC for high data rate

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1765083A1 (de) 1968-03-29 1971-07-01 Siemens Ag Verfahren zum Herstellen von Traegern zum Aufnehmen und Verbinden elektrischer Bauelemente
DE1930642A1 (de) 1969-06-18 1971-01-07 Siemens Ag Leiterplatte zum Aufnehmen und Verbinden elektrischer Bauelemente
JPS5987893A (ja) 1982-11-12 1984-05-21 株式会社日立製作所 配線基板とその製造方法およびそれを用いた半導体装置
DE3709770A1 (de) 1987-03-25 1988-10-13 Ant Nachrichtentech Leiterplatte, -folie, multilayerinnenlage oder leitersubstrat mit durchkontaktierungen und herstellungsverfahren
JPH01124296A (ja) 1987-11-09 1989-05-17 Hitachi Chem Co Ltd 配線板の製造法
US5363275A (en) * 1993-02-10 1994-11-08 International Business Machines Corporation Modular component computer system
JP3684239B2 (ja) * 1995-01-10 2005-08-17 株式会社 日立製作所 低ｅｍｉ電子機器
JPH10270809A (ja) 1997-03-28 1998-10-09 Hoya Corp 配線基板およびその製造方法
US6075427A (en) * 1998-01-23 2000-06-13 Lucent Technologies Inc. MCM with high Q overlapping resonator
JPH11233917A (ja) 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc 積層基板の製造方法
CA2295576A1 (en) 1998-05-06 1999-11-11 Ngk Insulators, Ltd. Substrate material for printed circuit, process for production thereof, and intermediate block for said substrate material
US6165892A (en) * 1998-07-31 2000-12-26 Kulicke & Soffa Holdings, Inc. Method of planarizing thin film layers deposited over a common circuit base

Also Published As

Publication number Publication date
KR20030064423A (ko) 2003-07-31
WO2002051222A3 (en) 2003-02-06
ATE395807T1 (de) 2008-05-15
US6632734B2 (en) 2003-10-14
EP1344435A2 (de) 2003-09-17
US20030127742A1 (en) 2003-07-10
CN1543757A (zh) 2004-11-03
KR100550298B1 (ko) 2006-02-08
US6563210B2 (en) 2003-05-13
EP1344435B1 (de) 2008-05-14
HK1058283A1 (en) 2004-05-07
JP2004527898A (ja) 2004-09-09
US20020074644A1 (en) 2002-06-20
AU2002228674A1 (en) 2002-07-01
MY123629A (en) 2006-05-31
WO2002051222A2 (en) 2002-06-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806