HK1010072A1 - Flash memory - Google Patents

Flash memory Download PDF

Info

Publication number
HK1010072A1
HK1010072A1 HK98110569A HK98110569A HK1010072A1 HK 1010072 A1 HK1010072 A1 HK 1010072A1 HK 98110569 A HK98110569 A HK 98110569A HK 98110569 A HK98110569 A HK 98110569A HK 1010072 A1 HK1010072 A1 HK 1010072A1
Authority
HK
Hong Kong
Prior art keywords
voltage
memory cells
word lines
source
erasure
Prior art date
Application number
HK98110569A
Other languages
German (de)
English (en)
French (fr)
Chinese (zh)
Other versions
HK1010072B (en
Inventor
Siba Kazuyosi
Terasawa Masaaki
Original Assignee
Hitachi Ltd
Hitachi Vlsi Engineering Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP01809593A external-priority patent/JP3489845B2/ja
Application filed by Hitachi Ltd, Hitachi Vlsi Engineering Corporation filed Critical Hitachi Ltd
Publication of HK1010072B publication Critical patent/HK1010072B/en
Publication of HK1010072A1 publication Critical patent/HK1010072A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Landscapes

  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
HK98110569A 1992-03-26 1998-09-10 Flash memory HK1010072A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP6809992 1992-03-26
JP68099/92 1992-03-26
JP01809593A JP3489845B2 (ja) 1992-03-26 1993-01-08 フラッシュメモリ、及びデータプロセッサ
JP18095/93 1993-01-08

Publications (2)

Publication Number Publication Date
HK1010072B HK1010072B (en) 1999-06-11
HK1010072A1 true HK1010072A1 (en) 1999-06-11

Family

ID=26354720

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98110569A HK1010072A1 (en) 1992-03-26 1998-09-10 Flash memory

Country Status (3)

Country Link
EP (1) EP0562737B1 (cs)
DE (1) DE69319162T2 (cs)
HK (1) HK1010072A1 (cs)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0756286B1 (en) 1995-07-24 2000-01-26 STMicroelectronics S.r.l. Flash EEPROM with on-chip erase source voltage generator
DE69521203T2 (de) * 1995-07-31 2006-01-12 Stmicroelectronics S.R.L., Agrate Brianza Flash-EEPROM mit gesteuerter Entladungszeit der Wortleitungs- und Sourcespannungen nach der Löschung
KR970051170A (ko) * 1995-12-29 1997-07-29 김주용 메모리 셀 어레이 및 그를 이용한 프로그램 방법
US5995417A (en) * 1998-10-20 1999-11-30 Advanced Micro Devices, Inc. Scheme for page erase and erase verify in a non-volatile memory array
JP3976774B1 (ja) 2006-03-10 2007-09-19 株式会社Ｇｅｎｕｓｉｏｎ 不揮発性半導体記憶装置およびその制御方法
WO2017200883A1 (en) 2016-05-17 2017-11-23 Silicon Storage Technology, Inc. Deep learning neural network classifier using non-volatile memory array
KR102384654B1 (ko) 2016-05-17 2022-04-11 실리콘 스토리지 테크놀로지 인크 개별 메모리 셀 판독, 프로그래밍, 및 소거를 갖는 3-게이트 플래시 메모리 셀들의 어레이
US10269440B2 (en) * 2016-05-17 2019-04-23 Silicon Storage Technology, Inc. Flash memory array with individual memory cell read, program and erase
US10580492B2 (en) 2017-09-15 2020-03-03 Silicon Storage Technology, Inc. System and method for implementing configurable convoluted neural networks with flash memories
US10803943B2 (en) 2017-11-29 2020-10-13 Silicon Storage Technology, Inc. Neural network classifier using array of four-gate non-volatile memory cells
US10748630B2 (en) 2017-11-29 2020-08-18 Silicon Storage Technology, Inc. High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
US11087207B2 (en) 2018-03-14 2021-08-10 Silicon Storage Technology, Inc. Decoders for analog neural memory in deep learning artificial neural network
US10699779B2 (en) 2017-11-29 2020-06-30 Silicon Storage Technology, Inc. Neural network classifier using array of two-gate non-volatile memory cells
US11409352B2 (en) 2019-01-18 2022-08-09 Silicon Storage Technology, Inc. Power management for an analog neural memory in a deep learning artificial neural network
US11023559B2 (en) 2019-01-25 2021-06-01 Microsemi Soc Corp. Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
US11270771B2 (en) 2019-01-29 2022-03-08 Silicon Storage Technology, Inc. Neural network classifier using array of stacked gate non-volatile memory cells
US11423979B2 (en) 2019-04-29 2022-08-23 Silicon Storage Technology, Inc. Decoding system and physical layout for analog neural memory in deep learning artificial neural network

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949309A (en) * 1988-05-11 1990-08-14 Catalyst Semiconductor, Inc. EEPROM utilizing single transistor per cell capable of both byte erase and flash erase
JPH02176882A (ja) * 1988-12-28 1990-07-10 Toshiba Corp 半導体集積回路
JP2601931B2 (ja) * 1990-04-06 1997-04-23 株式会社東芝 半導体不揮発性メモリ装置

Also Published As

Publication number Publication date
EP0562737A3 (cs) 1995-08-09
EP0562737A2 (en) 1993-09-29
DE69319162D1 (de) 1998-07-23
EP0562737B1 (en) 1998-06-17
DE69319162T2 (de) 1999-03-25

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20050310