HK1003665A1 - Method and apparatus for determining wait states on a per cycle basis in a data processing system - Google Patents

Method and apparatus for determining wait states on a per cycle basis in a data processing system

Info

Publication number
HK1003665A1
HK1003665A1 HK98102809A HK98102809A HK1003665A1 HK 1003665 A1 HK1003665 A1 HK 1003665A1 HK 98102809 A HK98102809 A HK 98102809A HK 98102809 A HK98102809 A HK 98102809A HK 1003665 A1 HK1003665 A1 HK 1003665A1
Authority
HK
Hong Kong
Prior art keywords
data processing
processing system
per cycle
cycle basis
wait states
Prior art date
Application number
HK98102809A
Other languages
English (en)
Inventor
Michael I Catherwood
Norrie R Robertson
Gordon W Mckinnon
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of HK1003665A1 publication Critical patent/HK1003665A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
HK98102809A 1996-05-09 1998-04-02 Method and apparatus for determining wait states on a per cycle basis in a data processing system HK1003665A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/645,014 US5854944A (en) 1996-05-09 1996-05-09 Method and apparatus for determining wait states on a per cycle basis in a data processing system

Publications (1)

Publication Number Publication Date
HK1003665A1 true HK1003665A1 (en) 1998-11-06

Family

ID=24587295

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98102809A HK1003665A1 (en) 1996-05-09 1998-04-02 Method and apparatus for determining wait states on a per cycle basis in a data processing system

Country Status (5)

Country Link
US (1) US5854944A (xx)
EP (1) EP0806729B1 (xx)
JP (1) JP3740250B2 (xx)
DE (1) DE69710515T2 (xx)
HK (1) HK1003665A1 (xx)

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US6356987B1 (en) * 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states
US6754885B1 (en) 1999-05-17 2004-06-22 Invensys Systems, Inc. Methods and apparatus for controlling object appearance in a process control configuration system
US7089530B1 (en) 1999-05-17 2006-08-08 Invensys Systems, Inc. Process control configuration system with connection validation and configuration
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US6788980B1 (en) 1999-06-11 2004-09-07 Invensys Systems, Inc. Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an IP network
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US6779128B1 (en) 2000-02-18 2004-08-17 Invensys Systems, Inc. Fault-tolerant data transfer
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US7778717B2 (en) 2002-04-15 2010-08-17 Invensys Systems, Inc. Component object model communication method for a control system
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US7075546B2 (en) * 2003-04-11 2006-07-11 Seiko Epson Corporation Intelligent wait methodology
US7761923B2 (en) 2004-03-01 2010-07-20 Invensys Systems, Inc. Process control methods and apparatus for intrusion detection, protection and network hardening
WO2007123753A2 (en) 2006-03-30 2007-11-01 Invensys Systems, Inc. Digital data processing apparatus and methods for improving plant performance
US8594814B2 (en) 2008-06-20 2013-11-26 Invensys Systems, Inc. Systems and methods for immersive interaction with actual and/or simulated facilities for process, environmental and industrial control
US8463964B2 (en) 2009-05-29 2013-06-11 Invensys Systems, Inc. Methods and apparatus for control configuration with enhanced change-tracking
US8127060B2 (en) 2009-05-29 2012-02-28 Invensys Systems, Inc Methods and apparatus for control configuration with control objects that are fieldbus protocol-aware
US9405720B2 (en) * 2013-03-15 2016-08-02 Atmel Corporation Managing wait states for memory access

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Also Published As

Publication number Publication date
EP0806729B1 (en) 2002-02-20
DE69710515T2 (de) 2002-07-18
EP0806729A1 (en) 1997-11-12
JPH1091579A (ja) 1998-04-10
JP3740250B2 (ja) 2006-02-01
DE69710515D1 (de) 2002-03-28
US5854944A (en) 1998-12-29

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Legal Events

Date Code Title Description
PF Patent in force
AS Change of ownership

Owner name: FREESCALE SEMICONDUCTOR, INC.

Free format text: FORMER OWNER(S): MOTOROLA INC

PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20080416