GB762823A - Improvements in or relating to electric circuits - Google Patents

Abstract

762,823. Non-contact-making relays. PHILIPS ELECTRICAL INDUSTRIES, Ltd. Oct. 13, 1954 [Oct. 15, 1953], No. 29499/54. Class 40 (4). An AND or OR gate comprises a number of saturable cores each having two windings, one winding being connected to a common alternating or pulse source while the other is associated with an individual input. As shown in Fig. 1, an AND gate comprises saturable cores 1, 2 and 3 having input windings a, band c connected to sources I, II and III respectively, and output windings A, B and C arranged in series with an impedance R and a low-impedance alternating voltage or pulse source G. In this arrangement an effective output voltage u is produced across R only when all the cores are saturated simultaneously by currents in their respective input windings. When the inputs comprise pulses they are synchronized with the pulse source G. In a modification, Fig. 4, the impedance R is omitted and an inverse AND output u of zero value is obtained across the series-connected windings A, B, C under the same conditions, a current pulse source GC of high internal impedance being employed in this case. If the windings A, B and C are connected in parallel the arrangement constitutes an OR gate, Fig. 3, in which a zero output across impedance R is obtained only when inputs from I, II and III are simultaneously zero. An inverse OR output is obtained when the circuit comprising the windings A, B and C is arranged as in Fig. 6. The cores may alternatively constitute saturable transformers, the windings A, B and C being coupled with a separate output circuit. This modification as applied to the inverse AND arrangement shown in Fig. 4 is illustrated in Fig. 5, the output u being obtained across series-connected secondary windings A', B<SP>1</SP> and C<SP>1</SP>. Series or parallel connections of the windings A, B, C and A<SP>1</SP>, B<SP>1</SP>, C<SP>1</SP> may be used, Figs. 7 to 9 (not shown). The transformer arrangements may be further modified by the use of three-legged cores 4, 5, 6, Fig. 10, and divided windings A, B, C which are then magnetically decoupled from the input windings a, b, c. The arrangement illustrated constitutes an AND gate. To ensure that an effective zero output is obtained under the appropriate conditions, Fig. 11, the combined voltage induced in windings A<SP>1</SP>, B<SP>1</SP>, C<SP>1</SP> when all the cores are saturated may be opposed by an equal and opposite voltage injected by a transformer 10.