GB678162A - Improvements in or relating to frequency dividers - Google Patents

Abstract

678,162. Valve frequency-dividing circuits. MARCONI'S WIRELESS TELEGRAPH CO., Ltd. Dec. 22,1949 [Jan. 21, 1949], No. 1779/49. Class 40 (vi). In a frequency divider comprising a cascaded connection of divider stages an output frequency is obtained which has the phase stability of the input frequency by connecting a point in each divider stage through an impedance to a common load fed from a rectifier so that the voltages at these points pass through a negative (or positive peak) simultaneously and the output of every stage is in effect gated by the succeeding stages. The Figure shows a frequency divider comprising four stages of the type described in Specification 663,657. The input voltage is applied across inductor K and the tuned circuit L, C of each stage is tuned to the output frequency of that stage. A point on the tuned circuit of each stage is connected via a resistor R2 to a common lead W so that the voltages derived from each stage pass through a negative peak simultaneously and rectifier D is biased to conduct on the peak of the aggregate of these voltages. The output from each stage is thus effectively gated by the succeeding stage and an output pulse train at the required divided frequency is produced across load LR. An amplifier AM may be interposed between the common lead W and rectifier D. In a modification the output frequency of the divider chain synchronizes a flip-flop or similar circuit, the pulse output of which is filtered to give a sinusoidal output voltage. A number of additional divider stages may be interposed which are not connected to the common rectifier circuit.