GB2383697A - Method of speeding lock of PLL - Google Patents

Method of speeding lock of PLL Download PDF

Info

Publication number
GB2383697A
GB2383697A GB0130989A GB0130989A GB2383697A GB 2383697 A GB2383697 A GB 2383697A GB 0130989 A GB0130989 A GB 0130989A GB 0130989 A GB0130989 A GB 0130989A GB 2383697 A GB2383697 A GB 2383697A
Authority
GB
United Kingdom
Prior art keywords
phase
output
input
register
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0130989A
Other languages
English (en)
Other versions
GB0130989D0 (en
Inventor
Der Valk Robert Laurentius Van
Rijk Johannes Hermanus Aloy De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor ULC
Original Assignee
Zarlink Semoconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zarlink Semoconductor Inc filed Critical Zarlink Semoconductor Inc
Priority to GB0130989A priority Critical patent/GB2383697A/en
Publication of GB0130989D0 publication Critical patent/GB0130989D0/en
Priority to US10/326,213 priority patent/US6784706B2/en
Priority to DE10260454A priority patent/DE10260454A1/de
Priority to KR1020020085016A priority patent/KR20030057454A/ko
Priority to FR0216771A priority patent/FR2834395A1/fr
Priority to CNB021596069A priority patent/CN1211930C/zh
Publication of GB2383697A publication Critical patent/GB2383697A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
GB0130989A 2001-12-27 2001-12-27 Method of speeding lock of PLL Withdrawn GB2383697A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
GB0130989A GB2383697A (en) 2001-12-27 2001-12-27 Method of speeding lock of PLL
US10/326,213 US6784706B2 (en) 2001-12-27 2002-12-20 Method of stabilizing phase-locked loop
DE10260454A DE10260454A1 (de) 2001-12-27 2002-12-21 Verfahren zum Stabilisieren einer phasenverriegelten Schleife
KR1020020085016A KR20030057454A (ko) 2001-12-27 2002-12-27 위상 고정 루프의 안정화 방법
FR0216771A FR2834395A1 (fr) 2001-12-27 2002-12-27 Procede et dispositif de stabilisation d'une boucle a verrouillage de phase
CNB021596069A CN1211930C (zh) 2001-12-27 2002-12-27 稳定锁相环的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0130989A GB2383697A (en) 2001-12-27 2001-12-27 Method of speeding lock of PLL

Publications (2)

Publication Number Publication Date
GB0130989D0 GB0130989D0 (en) 2002-02-13
GB2383697A true GB2383697A (en) 2003-07-02

Family

ID=9928419

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0130989A Withdrawn GB2383697A (en) 2001-12-27 2001-12-27 Method of speeding lock of PLL

Country Status (6)

Country Link
US (1) US6784706B2 (de)
KR (1) KR20030057454A (de)
CN (1) CN1211930C (de)
DE (1) DE10260454A1 (de)
FR (1) FR2834395A1 (de)
GB (1) GB2383697A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2702421A4 (de) * 2011-04-29 2015-11-25 Analog Devices Inc System und verfahren zur erkennung einer grundfrequenz in einem stromsystem

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145399B2 (en) * 2002-06-19 2006-12-05 Texas Instruments Incorporated Type-II all-digital phase-locked loop (PLL)
US7421043B2 (en) * 2002-11-27 2008-09-02 Lsi Corporation Method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms
US7196588B2 (en) * 2005-07-22 2007-03-27 Mediatek Incorporation Auto-gain controlled digital phase-locked loop and method thereof
US7369002B2 (en) * 2005-07-28 2008-05-06 Zarlink Semiconductor, Inc. Phase locked loop fast lock method
US7482883B2 (en) * 2005-10-19 2009-01-27 Texas Instruments Incorporated Gain normalization of a digitally controlled oscillator in an all digital phase locked loop based transmitter
US9072897B2 (en) 2007-03-09 2015-07-07 Mainstay Medical Limited Systems and methods for restoring muscle function to the lumbar spine
US8054931B2 (en) * 2007-08-20 2011-11-08 Agere Systems Inc. Systems and methods for improved timing recovery
CN101498761B (zh) * 2008-02-02 2011-11-16 北京芯慧同用微电子技术有限责任公司 锁相环系统的阶跃响应性能的测试方法
CN101533099B (zh) * 2009-03-22 2011-08-31 中国科学院近代物理研究所 电荷频率转换器
WO2011112773A2 (en) 2010-03-11 2011-09-15 Mainstay Medical, Inc. Modular stimulator for treatment of back pain, implantable rf ablation system and methods of use
US9950159B2 (en) 2013-10-23 2018-04-24 Mainstay Medical Limited Systems and methods for restoring muscle function to the lumbar spine and kits for implanting the same
AU2012290152B2 (en) 2011-08-02 2016-08-11 Mainstay Medical Limited Apparatus for anchoring electrode leads for use with implantable neuromuscular electrical stimulator
US10425117B2 (en) 2011-11-30 2019-09-24 Maxlinear Asia Singapore PTE LTD Split microwave backhaul architecture with smart outdoor unit
US9380645B2 (en) 2011-11-30 2016-06-28 Broadcom Corporation Communication pathway supporting an advanced split microwave backhaul architecture
US9621330B2 (en) 2011-11-30 2017-04-11 Maxlinear Asia Singapore Private Limited Split microwave backhaul transceiver architecture with coaxial interconnect
US10195419B2 (en) 2012-06-13 2019-02-05 Mainstay Medical Limited Electrode leads for use with implantable neuromuscular electrical stimulator
US8704566B2 (en) * 2012-09-10 2014-04-22 International Business Machines Corporation Hybrid phase-locked loop architectures
CN102984878B (zh) * 2012-11-28 2015-04-29 中国原子能科学研究院 医用回旋加速器的多态调谐方法
US8957711B2 (en) * 2013-04-29 2015-02-17 Microsemi Semiconductor Ulc Phase locked loop with precise phase and frequency slope limiter
US10471268B2 (en) 2014-10-16 2019-11-12 Mainstay Medical Limited Systems and methods for monitoring muscle rehabilitation
US9634675B2 (en) * 2015-03-31 2017-04-25 Microsemi Semiconductor Ulc Phase locked loop with jump-free holdover mode
US10327810B2 (en) 2016-07-05 2019-06-25 Mainstay Medical Limited Systems and methods for enhanced implantation of electrode leads between tissue layers
US10735007B1 (en) * 2019-05-28 2020-08-04 Harris Global Communications, Inc. Method of limiting frequency overshoot in a timing recovery loop
CN113472346B (zh) * 2021-05-27 2023-08-04 沈阳大学 一种基于复合型滤波器的电网同步软件锁相环

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5651037A (en) * 1995-10-04 1997-07-22 Motorola, Inc. Apparatus for preforming discrete-time analog queuing and computing in a communication system
GB2328095A (en) * 1997-05-16 1999-02-10 Samsung Electronics Co Ltd Reducing lock-up time of a frequency synthesiser

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT986172B (it) * 1973-06-18 1975-01-20 Fatme Spa Dispositivo di sincronizzazione automatica per un oscillatore in particolare per impianti di tele comunicazione
US4587496A (en) * 1984-09-12 1986-05-06 General Signal Corporation Fast acquisition phase-lock loop
US4974221A (en) * 1987-07-17 1990-11-27 Canon Kabushiki Kaisha Method and apparatus for reproducing information by varying a sensitivity of a phase-locked loop in accordance with a detection state of a reproduced signal
US5555276A (en) * 1990-01-18 1996-09-10 Norand Corporation Method of and apparatus for controlling modulation of digital signals in frequency-modulated transmissions
US5161175A (en) * 1991-05-28 1992-11-03 Motorola, Inc. Circuit and method of detecting an invalid clock signal
US5260979A (en) * 1991-05-28 1993-11-09 Codex Corp. Circuit and method of switching between redundant clocks for a phase lock loop
US5498998A (en) * 1992-11-16 1996-03-12 Gehrke; James K. Method for adjusting the output frequency of a frequency synthesizer
US5334952A (en) * 1993-03-29 1994-08-02 Spectralink Corporation Fast settling phase locked loop
US5534823A (en) * 1994-02-28 1996-07-09 Nec Corporation Phase locked loop (PLL) circuit having variable loop filter for shortened locking time
US5926515A (en) * 1995-12-26 1999-07-20 Samsung Electronics Co., Ltd. Phase locked loop for improving a phase locking time
EP0831483B1 (de) * 1996-09-24 2002-08-28 Hewlett-Packard Company, A Delaware Corporation Datenverarbeitungsgerät und -verfahren
US6018556A (en) * 1996-11-21 2000-01-25 Dsp Group, Inc. Programmable loop filter for carrier recovery in a radio receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5651037A (en) * 1995-10-04 1997-07-22 Motorola, Inc. Apparatus for preforming discrete-time analog queuing and computing in a communication system
GB2328095A (en) * 1997-05-16 1999-02-10 Samsung Electronics Co Ltd Reducing lock-up time of a frequency synthesiser

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2702421A4 (de) * 2011-04-29 2015-11-25 Analog Devices Inc System und verfahren zur erkennung einer grundfrequenz in einem stromsystem
US9696355B2 (en) 2011-04-29 2017-07-04 Analog Devices, Inc. System and method for detecting a fundamental frequency of an electric power system

Also Published As

Publication number Publication date
KR20030057454A (ko) 2003-07-04
GB0130989D0 (en) 2002-02-13
CN1431780A (zh) 2003-07-23
US6784706B2 (en) 2004-08-31
CN1211930C (zh) 2005-07-20
DE10260454A1 (de) 2003-07-17
FR2834395A1 (fr) 2003-07-04
US20030137329A1 (en) 2003-07-24

Similar Documents

Publication Publication Date Title
GB2383697A (en) Method of speeding lock of PLL
KR100332246B1 (ko) Ｄｌｌ 교정 위상 멀티플렉서 및 보간기
EP0652642B1 (de) Phasenregelschleife mit Überbrückungsmodus
US10256967B2 (en) Clock and data recovery circuit with jitter tolerance enhancement
EP2903163B1 (de) Vorrichtung und Verfahren zum Holdover von Signalunterbrechung bei einer Schnellladungspumpe
US20190384351A1 (en) Hitless switching when generating an output clock derived from multiple redundant input clocks
CA2004842C (en) Phase-lock loop circuit with improved output signal jitter performance
US20140266338A1 (en) Biased bang-bang phase detector for clock and data recovery
WO1995033320A1 (en) Cell-based clock recovery device
US10840950B2 (en) Adaptive channelizer
US7197102B2 (en) Method and apparatus for clock-and-data recovery using a secondary delay-locked loop
EP2824657A1 (de) Punkt-zu-Mehrpunkt-Taktweitergleitete Signalisierung für große Anzeigen
US20110026650A1 (en) Rapid Sampling Phase Recovery
US6538518B1 (en) Multi-loop phase lock loop for controlling jitter in a high frequency redundant system
US5815017A (en) Forced oscillator circuit and method
FI107093B (fi) Integroidun oskillaattorin automaattinen virittäminen
US10348312B1 (en) Circuit for and method of implementing a bursty clock and data recovery circuit using an eyescan detection circuit
US8310288B2 (en) PLL circuit
CN112994687B (zh) 一种参考时钟信号注入锁相环电路及消除失调方法
KR100302893B1 (ko) 인터리브 위상 검출기를 이용한 1000ｍｂ 위상 피커 클럭 복구구조
US5670913A (en) Phase locked loop circuit with false locking detector and a lock acquisition sweep
KR100431716B1 (ko) 지연 동기 루프를 이용한 디지털 주파수 편이 복조기 및복조 방법
CN112019212A (zh) 锁相环中的参考时钟频率变化处理
KR100531457B1 (ko) 다 위상 클럭신호 발생을 위한 발진기가 배제된 지연 동기루프
EP2727246A2 (de) Jitterunterdrückung bei typ-i-dll

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)