GB2374726A - Stacked structure of an image sensor having image sensing chip located above integrated circuit - Google Patents

Stacked structure of an image sensor having image sensing chip located above integrated circuit Download PDF

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Publication number
GB2374726A
GB2374726A GB0109827A GB0109827A GB2374726A GB 2374726 A GB2374726 A GB 2374726A GB 0109827 A GB0109827 A GB 0109827A GB 0109827 A GB0109827 A GB 0109827A GB 2374726 A GB2374726 A GB 2374726A
Authority
GB
United Kingdom
Prior art keywords
image sensor
substrate
package structure
integrated circuit
stacked package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0109827A
Other versions
GB0109827D0 (en
Inventor
Hsiu Wen Tu
Wen Chuan Chen
Mon Nan Ho
Li Huan Chen
Nai Hua Yeh
Yen Cheng Huang
Yung Sheng Chiu
Wen Tsan Lee
Joe Liu
Wu Hsiang Lee
Meng Ru Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kingpak Technology Inc
Original Assignee
Kingpak Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kingpak Technology Inc filed Critical Kingpak Technology Inc
Priority to GB0109827A priority Critical patent/GB2374726A/en
Priority to DE20109202U priority patent/DE20109202U1/en
Priority to DE10122724A priority patent/DE10122724A1/en
Priority claimed from DE10122724A external-priority patent/DE10122724A1/en
Publication of GB0109827D0 publication Critical patent/GB0109827D0/en
Publication of GB2374726A publication Critical patent/GB2374726A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Facsimile Heads (AREA)

Abstract

A stacked package structure of an image sensor for electrically connecting to a printed circuit board (20) includes substrate (10), integrated circuit (22), image sensing chip (26) and transparent layer (32). The substrate (10) has first surface (12) formed with signal input terminals (16) and second surface (14) formed with signal output terminals (18) for electrical connection to the printed circuit board (20). The integrated circuit (22) is mounted on the first surface (12) of the substrate (10) and is connected to the signal input terminals (16). The image sensing chip (26) is located above the integrated circuit (22) to form a stacked structure for connection with the signal input terminals (16). A spacer (28) may be provided between the integrated circuit (22) and the image sensing chip (26) to form gap (30). The transparent layer (32) is arranged above the image sensing chip (26) enabling the image sensing chip (26) to receive signals.

Description

<Desc/Clms Page number 1>
STACKED PACKAGE STRUCTURE OF IMAGE SENSOR BACKGROUND OF THE INVENTION Field of the invention The invention relates to a stacked structure of an image sensor, in particular, to a structure in which integrated circuits and image sensing chips, both having different functions, are packaged into a package body so as to reduce the number of package substrates and to integrally package the integrated circuits and image sensing chips both having different functions.
Description of the related art A general sensor is used for sensing signals, which may be optical or audio signals. The sensor of the invention is used for receiving image signals and transforming the image signals into electrical signals that are transmitted to a printed circuit board.
A general image sensor is used for receiving image signals and converting the image signals into electrical signals that are transmitted to a printed circuit board. The image sensor is then electrically connected to other integrated circuits to have any required functions. For example, the image sensor may be electrically connected to a digital signal processor that processes the signals generated from the image sensor. Further, the image sensor may also be electrically connected to a micro controller, a central processor, or the like. so as to have any required functions.
However, since the conventional image sensor is packaged. the integrated circuits corresponding to the image sensor have to be individually packaged with the image sensor. Then, the packaged image sensor and various signal processing units are electrically connected onto the printed circuit board.
<Desc/Clms Page number 2>
Thereafter, the image sensor is electrically connected to the signal processing units by a plurality of wirings, respectively. Therefore, in order to individually package each of the signal processing units and the image sensor, a plurality of substrate and package bodies have to be used, thereby increasing the manufacturing costs. Furthermore, the required area of the printed circuit board should be larger when mounting each of the signal processing units onto the printed circuit board, so the products cannot be made small, thin, and slight.
In order to solve the above-mentioned problems, the invention provides a stacked structure of an image sensor to overcome the disadvantages caused by the conventional image sensor.
SUMMARY OF THE INVENTION It is therefore an object of the invention to provide a stacked package structure of an image sensor for reducing the number of packaged elements and lowering the package costs.
It is therefore another object of the invention to provide a stacked package structure of an image sensor for simplifying and facilitating the manufacturing processes.
It is therefore still another object of the invention to provide a stacked package structure of an image sensor for reducing the area of the image sensing products.
It is therefore yet another object of the invention to provide a packaged package structure of an image sensor for lowering the package costs and testing costs of the image sensing products.
According to one aspect of the invention, a stacked structure of an image sensor for electrically connecting to a printed circuit board includes a substrate. an
<Desc/Clms Page number 3>
integrated circuit, an image sensing chip, and a transparent layer. The substrate has a first surface and a second surface opposite to the first surface. The first surface is formed with signal input terminals. The second surface is formed with signal output terminals for electrically connecting the substrate to the printed circuit board. The integrated circuit is mounted on the first surface of the substrate and electrically connected to the signal input terminals of the substrate.
The image sensing chip is located above the integrated circuit to form a stacked structure with the integrated circuit and is used for electrically connecting to the signal input terminals of the substrate. The transparent layer covers the image sensing chip. The image sensing chip receives image signals via the transparent layer and converts the image signals into electrical signals that are to be transmitted to the substrate.
Thus, the image sensing chip of the image sensing product and the integrated circuit can be integrally packaged.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a stacked package structure of an image sensor in accordance with a first embodiment of the invention.
FIG. 2 shows a stacked package structure of an image sensor in accordance with a second embodiment of the invention.
FIG. 3 shows a stacked package structure of an image sensor in accordance with a third embodiment of the invention.
FIG. 4 shows a stacked package structure of an image sensor in accordance with a fourth embodiment of the invention.
DETAIL DESCRIPTION OF THE INVENTION
<Desc/Clms Page number 4>
Referring to FIG. 1, the stacked package structure of the image sensor includes a substrate 10, an integrated circuit 22, an image sensing chip 26. a projection layer 34, and a transparent layer 36.
The substrate 10 has a first surface 12 and a second surface 14 opposite to the first surface 12. The first surface 12 is formed with signal input terminals 16.
The second surface 14 is formed with signal output terminals 18, which may be metallic balls arranged in the form of a ball grid array, for electrically connecting to a printed circuit board 20. Thus, the signals form the substrate 10 can be transmitted to the printed circuit board 20.
The integrated circuit 22 may be a signal processing unit such as a digital signal processor, a micro processor, a central processing unit (CPU), or the like. The integrated circuit 22 is arranged on the first surface 12 of the substrate 10 and is electrically connected to the signal input terminals 16 of the substrate 10 by way of wire bonding. Thus, the integrated circuit 22 can be electrically connected to the substrate 10 for transmitting the signals from the integrated circuit 22 to the substrate 10.
The image sensing chip 26 is arranged above the integrated circuit 22 to L-r form a stacked structure with the integrated circuit 22. In order to prevent the metal wirings 24 located above the integrated circuit 22 from being pressed by the image sensing chip 26. a spacer 28 is provided between the integrated circuit 22 and the image sensing chip 26 to form a gap 30 therebetween. Thus, parts of the metal wirings 24 are located within the gap 30. The image sensing chip 26 is electrically connected to the signal input terminals 16 of the substrate 10 by the metal wirings 32. Thus, the image sensing chip 26 is electrically connected to the substrate 10 so that the signals form the image sensing chip 26 can be transmitted to the substrate 10. If the integrated circuit 22 is a digital signal processor, the signals from the image sensing chip 26 can be processed in advance
<Desc/Clms Page number 5>
and then transmitted to the printed circuit board 20.
The projection layer 34 is a frame structure located on the first surface 12 of the substrate 10 for surrounding the integrated circuit 22 and the image sensing chip 26.
The transparent layer 36 may be a transparent glass covering the projection layer 34 for sealing the image sensing chip 26 and the integrated circuit 22. The image sensing chip 26 can receive image signals via the transparent layer 36 and convert the image signals into electrical signals that are to be transmitted to the substrate 10.
Referring to FIG. 2, the integrated circuit 22 is formed with electroconductive metals 38 electrically connecting to the signal input terminals 16 of the substrate 10 by way of flip chip bonding. Thus, the integrated circuit 22 is electrically connected to the substrate 10. The image sensing chip 26 is electrically connected to the signal input terminals 16 of the substrate 10 via the metal wirings 32 by way of wire bonding Referring to FIG. 3, the transparent layer is a transparent glue 40. After the image sensing chip 26 is stacked above the integrated circuit 22 and the image sensing chip 26 and the integrated circuit 22 are electrically connected to the substrate 10, a transparent glue 40 is provided for covering the image sensing chip 26 and the integrated circuit 22. Thus, the image sensing chip 26 also can receive image signals via the transparent glue 40 and convert the image signals into electrical signals that are to be transmitted to the substrate 10. The electrical signals are then processed by the integrated circuit 22.
Referring to FIG. 4, the transparent layer is a "n-shaped" transparent glue 40 having a supporting column 42 arranged on the first surface 12 of the substrate 10. The "n-shaped" transparent glue 40 can be formed by injection molding or
<Desc/Clms Page number 6>
press molding. After the integrated circuit 22 is electrically connected to the substrate 10 by way of flip chip bonding, the image sensing chip 26 is stacked above the integrated circuit 22. Then, the image sensing chip 26 is electrically connected to the substrate 10 via the metal wirings 32 by way of wire bonding.
Thereafter, the" n -shaped" transparent glue 40 is directly mounted on the first surface 12 of the first surface 12 for sealing the image sensing chip 26 and the integrated circuit 22. Thus, the image sensing chip 26 can receive image signals via the" n -shaped" transparent glue 40 and convert the image signals into electrical signals that are to be transmitted to the substrate.
According to the above-mentioned structure, the invention has the following advantages.
1. Since the image sensing chip 26 and the integrated circuit 22 can be integrally packaged, the material forming the substrate 10 can be reduced. thereby lowering the manufacturing costs of the image sensing products.
2. Since the image sensing chip 26 and the integrated circuit 22 can be integrally packaged, the area of the image sensing products can be reduced.
3. Since the image sensing chip 26 and the integrated circuit 22 can be integrally packaged, there is only one package body. Thus. only one testing fixture needs be used, and the testing costs can also be reduced.
4. Since the image sensing chip 26 and the integrated circuit 22 can be integrally packaged, two chips can be packaged by only one packaging process.
The package costs can thus be effectively lowered.
While the invention has been described by way of example and in terms of preferred embodiments. it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various
<Desc/Clms Page number 7>
modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.

Claims (14)

WHAT IS CLAIMED IS:
1. A stacked package structure of an image sensor for electrically connecting to a printed circuit board, comprising: a substrate having a first surface and a second surface opposite to the first surface, the first surface being formed with signal input terminals, the second surface being formed with signal output terminals for electrically connecting the substrate to the printed circuit board; an integrated circuit mounted on the first surface of the substrate and electrically connected to the signal input terminals of the substrate; an image sensing chip located above the integrated circuit to form a stacked structure with the integrated circuit and electrically connected to the signal input terminals of the substrate; and a transparent layer covering the image sensing chip, wherein the image sensing chip receives image signals via the transparent layer and converts the image signals into electrical signals that are to be transmitted to the substrate.
2. The stacked package structure of the image sensor according to claim 1. wherein the signal output terminals on the second surface of the substrate are metallic balls arranged in the form of a ball grid array for electrically connecting to the printed circuit board.
3. The stacked package structure of the image sensor according to claim 1. wherein the integrated circuit is a signal processing unit.
4. The stacked package structure of the image sensor according to claim 3. wherein the signal processing unit is a digital signal processor for processing the signals from the image sensing chip.
<Desc/Clms Page number 9>
5. The stacked package structure of the image sensor according to claim 3, wherein the signal processing unit is a micro controller.
6. The stacked package structure of the image sensor according to claim 3, wherein the signal processing unit is a central processing unit (CPU).
7. The stacked package structure of the image sensor according to claim 1, wherein the integrated circuit is electrically connected to the signal input terminals of the substrate via a plurality of wirings.
8. The stacked package structure of the image sensor according to claim 1, wherein the integrated circuit is electrically connected to the signal input terminals of the substrate by way of flip chip bonding.
9. The stacked package structure of the image sensor according to claim !, wherein the transparent layer is a transparent glass.
10. The stacked package structure of the image sensor according to claim 1. wherein a projection layer is arranged on the periphery of the first surface of the substrate, and the transparent layer is arranged on the projection layer.
11. The stacked package structure of the image sensor according to claim I, wherein the image sensing chip is electrically connected to the signal input terminals of the substrate via a plurality of metal wirings.
12. The stacked package structure of the image sensor according to claim 1. wherein the transparent layer is a transparent glue.
13. The stacked package structure of the image sensor according to claim I. wherein the transparent layer is a "n -shaped" transparent glue having a supporting column mounted on the first surface of the substrate.
14. A stacked package structure of an image sensor as hereinbefore described with reference to or as shown in the accompanying drawings.
GB0109827A 2001-04-20 2001-04-20 Stacked structure of an image sensor having image sensing chip located above integrated circuit Withdrawn GB2374726A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0109827A GB2374726A (en) 2001-04-20 2001-04-20 Stacked structure of an image sensor having image sensing chip located above integrated circuit
DE20109202U DE20109202U1 (en) 2001-04-20 2001-05-10 Stack arrangement for an image sensor module
DE10122724A DE10122724A1 (en) 2001-04-20 2001-05-10 Compact assembly forming component of image sensor, stacks and interconnects image sensor chip, integrated circuit and substrate on PCB

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0109827A GB2374726A (en) 2001-04-20 2001-04-20 Stacked structure of an image sensor having image sensing chip located above integrated circuit
DE20109202U DE20109202U1 (en) 2001-04-20 2001-05-10 Stack arrangement for an image sensor module
DE10122724A DE10122724A1 (en) 2001-04-20 2001-05-10 Compact assembly forming component of image sensor, stacks and interconnects image sensor chip, integrated circuit and substrate on PCB

Publications (2)

Publication Number Publication Date
GB0109827D0 GB0109827D0 (en) 2001-06-13
GB2374726A true GB2374726A (en) 2002-10-23

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GB0109827A Withdrawn GB2374726A (en) 2001-04-20 2001-04-20 Stacked structure of an image sensor having image sensing chip located above integrated circuit

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DE (1) DE20109202U1 (en)
GB (1) GB2374726A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012750A (en) * 1983-07-01 1985-01-23 Nippon Denso Co Ltd Mounting device for semiconductor element
US5051802A (en) * 1988-01-22 1991-09-24 Thomson-Csf Compact image sensor
WO1998003011A1 (en) * 1996-07-11 1998-01-22 Simage Oy Imaging apparatus having a large sensing area
EP0853237A1 (en) * 1997-01-14 1998-07-15 Infrared Integrated Systems Ltd. Sensors using detector arrays
US5955733A (en) * 1995-08-29 1999-09-21 Simage Oy Imaging support for removably mounting an image device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012750A (en) * 1983-07-01 1985-01-23 Nippon Denso Co Ltd Mounting device for semiconductor element
US5051802A (en) * 1988-01-22 1991-09-24 Thomson-Csf Compact image sensor
US5955733A (en) * 1995-08-29 1999-09-21 Simage Oy Imaging support for removably mounting an image device
WO1998003011A1 (en) * 1996-07-11 1998-01-22 Simage Oy Imaging apparatus having a large sensing area
EP0853237A1 (en) * 1997-01-14 1998-07-15 Infrared Integrated Systems Ltd. Sensors using detector arrays

Also Published As

Publication number Publication date
GB0109827D0 (en) 2001-06-13
DE20109202U1 (en) 2001-09-27

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