GB2374725A - Stacked structure having image sensing chip and integrated circuit arrange on opposite surfaces of a substrate - Google Patents

Stacked structure having image sensing chip and integrated circuit arrange on opposite surfaces of a substrate Download PDF

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Publication number
GB2374725A
GB2374725A GB0109826A GB0109826A GB2374725A GB 2374725 A GB2374725 A GB 2374725A GB 0109826 A GB0109826 A GB 0109826A GB 0109826 A GB0109826 A GB 0109826A GB 2374725 A GB2374725 A GB 2374725A
Authority
GB
United Kingdom
Prior art keywords
substrate
image sensor
package structure
stacked package
sensor according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0109826A
Other versions
GB0109826D0 (en
Inventor
Hsiu Wen Tu
Wen Chuan Chen
Mon Nan Ho
Li Huan Chen
Nai Hua Yeh
Yen Cheng Huang
Yung Sheng Chiu
Jichen Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kingpak Technology Inc
Original Assignee
Kingpak Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kingpak Technology Inc filed Critical Kingpak Technology Inc
Priority to GB0109826A priority Critical patent/GB2374725A/en
Priority to DE10122722A priority patent/DE10122722A1/en
Priority to DE20109196U priority patent/DE20109196U1/en
Priority claimed from DE10122722A external-priority patent/DE10122722A1/en
Publication of GB0109826D0 publication Critical patent/GB0109826D0/en
Publication of GB2374725A publication Critical patent/GB2374725A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A stacked structure of an image sensor for electrically connecting to a printed circuit board (20) includes substrate (10), integrated circuit (22), image sensing chip (26) and transparent layer (32). The substrate (10) has first surface (12) formed with signal input terminals (16) and second surface (14) formed with signal input terminals (17) and signal output terminals (18). The image sensing chip (26) is mounted on the first surface (12) of the substrate (10) and is connected to signal input terminals (16). The integrated circuit (22) is arranged on the second surface (14) of the substrate (10) and is connected to the signal input terminals (17). The integrated circuit (22) may be sealed to the second surface (14) by mould resin (25). The transparent layer (32) is arranged above the image sensing chip (26) enabling the image sensing chip (26) to receive signals. The signal output terminals (18) for connecting to the printed circuit board (20) may form a lead frame or a ball grid array.

Description

<Desc/Clms Page number 1>
STACKED PACKAGE STRUCTURE OF IMAGE SENSOR BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a stacked package structure of an image sensor, in particular, to a structure in which integrated circuit and image sensing chip, both having different function, are packaged into a package body so as to reduce the number of the package substrates and to integrally package the integrated circuited and image sensing chip both having different functions.
Description of the art A general sensor is used for sensing signals, which may be optical or audio signals. The sensor of the present invention is used for receiving images and transforming the image signals into electrical signal to be transmitted to a printed circuit board.
A general sensor is used for receiving image signals and converting the image signals into electrical signals that are transmitted to a printed circuit board. The image sensor is then electrically connected to other integrated circuit to have any required functions. For example, the image sensor may be electrically connected to a digital signal processor that processes the signals generated from the image sensor. Further, the image sensor may also be electrically connected to a micro controller, a central processor, or the like, so as to have any required function.
However, since the conventional image sensor is packaged, the integrated circuits corresponding to the image sensor have to be individually packaged with the image sensor. Then, the packaged image sensor and various signal processing units are electrically connected onto the printed circuit board.
Thereafter, the image sensor is electrically connected to the signal
<Desc/Clms Page number 2>
processing units by a plurality of wirings, respectively, therefore, in order to individually package each of the signal processing units and the image sensor, a plurality of substrates and package bodied have to be used, thereby increasing the manufacturing costs. Furthermore, the required area of the printed circuit board should be large when mounting each of the processing units onto the printed circuit board, so the products cannot be made small, thin, and light.
In order to solve the above-mention problems, the present invention provides a stacked structure of an image sensor to overcome the disadvantages caused by conventional sensor.
SUMMAYR OF THE PRESENT INVENTION It is therefore an object of the present invention to provide a stacked package structure of an image sensor for reducing the number of the package elements and lowering the package costs.
It is therefore another object of the present invention to provide a stacked package structure of an image sensor for simplifying and facilitating the manufacturing processes.
It is therefor still object of the present invention to provide a stacked package structure of an image sensor for lowering the area of the image sensor.
It is therefor yet object of the present invention to provide a stacked package structure of an image sensor for lowering the package costs and testing costs of the image sensing products.
According to one aspect of the present invention, a stacked package structure of an image sensor for electrically connecting to a printed circuit board comprises a substrate, an image sensing chip, an integrated circuit. and a transparent layer. The substrate has a first surface formed with signal input terminals. and a second surface formed with signal input terminals and signal output terminals, which is electrically connected to the printed circuit board. The
<Desc/Clms Page number 3>
image sensing chip is located on the first surface of the substrate and electrically connected to signal input terminals formed on the substrate. The integrated circuit is arranged on the second surface of the substrate and electrically connected to the signal output terminals formed on the second surface of the substrate. And the transparent layer covers over image sensing chip, which can receive image signals via the transparent layer and convert the image signals into electrical signals that are to be transmitted to the substrate.
Thus, the image sensing chip of the image sensing product and integrated circuit can be integrally package.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a schematic illustration showing a stacked package structure of an image sensor according to a first embodiment of the present invention.
FIG. 2 is a schematic illustration showing a stacked package structure of an image sensor according to a second embodiment of the present invention.
FIG. 3 is a schematic illustration showing a stacked package structure of an image sensor according to a third embodiment of the present invention.
DETAIL DESCRIPTION OF THE PRESENT INVENTION The embodiment of the present invention will now be described reference to the drowning.
Referring to FIG. l, the stacked package structure of an image sensor of the present invention includes a substrate 10, an integrated circuit 22. an image sensing chip 26, a projecting structure 30 and a transparent layer 32.
The substrate 10 has a first surface 12 and a second surface 14 opposite to the first surface 14. The first surface 12 of the substrate 10 is formed with signal input terminals 16 for transmitting signals from the image sensing chip 26 to the
<Desc/Clms Page number 4>
substrate 10. The second surface 14 is formed with signal input terminals 17 for transmitting signals from the integrated circuit 22 to the substrate 10. then the second surface 14 is also formed with signal output terminals 18. which may be metallic lead-frames for electrically connecting to the printed circuit board 20. Thus, the signals from the substrate 10 can be transmitted to the printed circuit board 20.
The integrated circuit 22 is signal unit such as a digital signal processing unit, a micro-processor, a central processor unit (CPU), or the like. The integrated circuit 22 is mounted on the second surface 14 of the substrate 10 and is electrically connected to signal input terminals 17 on the second surface 14 of the substrate 10 via a plurality of the wirings24 by way of wire bonding. So that the integrated circuit 22 can be electrically connected to the substrate 10. A mold resin 25 is sealed on the integrated circuit 22 to prevent the plurality of the wirings24.
The image sensing chip 26 is arranged on the first surface 12 of the substrate 10. and is electrically connected to the signal input terminals 16 on the first surface 12 of the substrate 10 via a plurality of wirings28 by wa\ of wire bond. So as to the image sensing chip 26 can be transmit the signals from the image sensitive chip 26 to the substrate 10. While the integrated circuit 22 is a digital signal processor, which can be processed the signals from the image sensing chip 26 and may be transmitted the signals to the printed circuit board 20.
A projecting structure 30 is a frame structure, which is mounted on the first surface 12 of the substrate 10 for surrounding the image sensing chip 26.
A transparent layer 32 may be a transparent glass, which is located on the projecting structure 30 to cover the image sensing chip26. So that the image sensing chip26 can receive an image signals via the transparent layer 32 and can transform the image signals into electrical signals that are to be transmitted to the
<Desc/Clms Page number 5>
substarte 10.
Please referring to FIG. 2 is a schematic illustration showing a stacked package structure of an image sensor according to a second embodiment of the present invention.
The second surface 14 of substrate 10 is formed with a cavity 34. Then, the integrated circuit 22 is located within the cavity 34, and is electrically connected to the signal input terminals 17 on the second surface 14 of the substrate 10 via a plurality of wirings24 by way of wire bonding. A mold resin25 is sealed on the integrated circuit 22 to prevent a plurality of the wirings24. The signal output terminals 18 on the second surface 14 of the substrate 10 are metallic balls arranged in the form of ball grid array for electrically connecting to the printed circuit board 20.
The image sensing chip 26 is located on the first surface 12 of the substrate 10, and is electrically connected to the signal input 16 on the first surface 12 of the substrate 10 via a plurality of wirings28 by way of wire bonding. Therefore. the image sensing chip 26 is electrically connected to the substrate 10. then transmitted the signals from the image sensing 26 to the substrate 10.
Referring to FIG. 3, the bonding pads of the integrated circuit 22 being formed with metallic connected point 36 for electrically connecting to signal input terminals 17 on the second surface 14 of the substrate 10 by way of flip-chip type.
Thus the integrated circuit 22 is electrically connected to the substrate 10. The signal output terminals 18 are metallic balls arranged in the form of ball grid array for electrically connecting to the printed circuit board 20.
The image sensing chip26 is located on the first surface 12 of the substrate 10, and is electrically connected to the signal input 16 of the substrate 10 via a plurality of wirings24 by way of wire bond. So as to the image sensing chip 26 is electrically connected to the substrate 10 for transmitting the signals from
<Desc/Clms Page number 6>
the image sensing chip26 to the substrate 10.
The projecting structure 30 is a frame structure, which is mounted on the first surface 12 of the substrate 10 for surrounding the image sensing chip26.
The transparent layer 32 may be a transparent glass, which is located on the projecting structure 30 to cover the image sensing chip26. So that the image sensing chip26 can receive image signals via the transparent layer32 and can transform the image signals into electrical signals transmitted to the substrate 10.
According to the above-mention structure, the following advantages can be obtained.
I. Since the image sensing chip 34 and integrated circuit 30 can be integrally
package. the material forming the substrate 10 can be reduced, thereby lowering Z-1 the manufacturing costs of the image sensing products.
2. Since the image sensing chip 34 and integrated circuit 30can be integrally package, the area of the image sensing products can be reduced.
3. Since the image sensing chip34 and integrated circuit 30can be integrally package, there is only one package body. Thus, one testing fixture needs be used. and the testing costs can also be reduced.
4. Since the image sensing chip 34 and integrated circuit 30can be integrally package. two chips can be package by only one packaging process. The package costs can thus effectively lowered.
While the present invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.

Claims (13)

  1. WHAT IS CLAIMED IS I. A stacked package structure of an image sensor for electrically connecting to the printed circuit board, comprising : a substrate having a first surface formed with signal input terminals, and a second surface formed with signal input terminals and signal output terminals for electrically connecting to the printed circuit board. an image sensing chip located on the first surface of the substrate and electrically connected to the signal input terminals on the first surface of the substrate. an integrated circuit located on the second surface of the substrate and electrically connected to the signal input terminals on the second surface of the substrate. and a transparent layer covered over the image sensing chip so that the image sensing chip receives image signals via the transparent layer, and transforms image signals into electrically signals transmitted to the substrate.
  2. 2. The stacked package structure of an image sensor according to claim !. wherein the signal output terminals on the second surface of the substrate are metallic lead-frame.
  3. 3. The stacked package structure of an image sensor according to claim 1, wherein the second surface of the substrate being formed with a cavity for locating the integrated circuit.
  4. 4. The stacked package structure of an image sensor according to claim'), wherein the signal output terminals on the second surface of the substrate are metallic balls arranged in the form of ball grid array for electrically connecting to the printed circuit board.
  5. 5. The stacked package structure of an image sensor according to claim I. wherein the signal output terminals on the second surface of the substrate are
    <Desc/Clms Page number 8>
    metallic balls arranged in the form of ball grid array for electrically connecting to the printed circuit board.
  6. 6. The stacked package structure of an image sensor according to claim 1, wherein the integrated circuit is a signals processing unit.
  7. 7. The stacked package structure of an image sensor according to claim6, wherein the signals processing unit is a digital signals processor for processing the signals form the image sensing chip.
  8. 8. The stacked package structure of an image sensor according to claim6, wherein the signals processing unit is a micro-controller.
  9. 9. The stacked package structure of an image sensor according to claim6, wherein the signals processing unit is a central processing unit (CPU).
  10. 10. The stacked package structure of an image sensor according to claim 1, wherein the integrated circuit is electrically connected to the signal input terminals on the second surface of the substrate by way of flip-chip type.
  11. 11. The stacked package structure of an image sensor according to claim 1, wherein the transparent layer is a transparent glass.
  12. 12. The stacked package structure of an image sensor according to claim 1. wherein the first surface of the substrate is formed with a projecting structure so as to the transparent layer is located on the projecting structure.
  13. 13. A stacked package structure of an image sensor substantially as hereinbefore described with reference to or as shown in the accompanying drawings.
GB0109826A 2001-04-20 2001-04-20 Stacked structure having image sensing chip and integrated circuit arrange on opposite surfaces of a substrate Withdrawn GB2374725A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0109826A GB2374725A (en) 2001-04-20 2001-04-20 Stacked structure having image sensing chip and integrated circuit arrange on opposite surfaces of a substrate
DE10122722A DE10122722A1 (en) 2001-04-20 2001-05-10 Stacked structure for an image sensor has substrates forming an enclosed space in which sensor is located
DE20109196U DE20109196U1 (en) 2001-04-20 2001-05-10 Stack arrangement for an image sensor module

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0109826A GB2374725A (en) 2001-04-20 2001-04-20 Stacked structure having image sensing chip and integrated circuit arrange on opposite surfaces of a substrate
DE10122722A DE10122722A1 (en) 2001-04-20 2001-05-10 Stacked structure for an image sensor has substrates forming an enclosed space in which sensor is located
DE20109196U DE20109196U1 (en) 2001-04-20 2001-05-10 Stack arrangement for an image sensor module

Publications (2)

Publication Number Publication Date
GB0109826D0 GB0109826D0 (en) 2001-06-13
GB2374725A true GB2374725A (en) 2002-10-23

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GB0109826A Withdrawn GB2374725A (en) 2001-04-20 2001-04-20 Stacked structure having image sensing chip and integrated circuit arrange on opposite surfaces of a substrate

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DE (1) DE20109196U1 (en)
GB (1) GB2374725A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104505393A (en) * 2014-09-16 2015-04-08 华天科技（昆山）电子有限公司 Back-illuminated image sensor three-dimensional stacked packaging structure and packaging technology
US10566369B2 (en) 2016-12-22 2020-02-18 UTAC Headquarters Pte. Ltd. Image sensor with processor package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0807976A2 (en) * 1996-05-17 1997-11-19 Sony Corporation Solid-state imaging apparatus and camera using the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0807976A2 (en) * 1996-05-17 1997-11-19 Sony Corporation Solid-state imaging apparatus and camera using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104505393A (en) * 2014-09-16 2015-04-08 华天科技（昆山）电子有限公司 Back-illuminated image sensor three-dimensional stacked packaging structure and packaging technology
US10566369B2 (en) 2016-12-22 2020-02-18 UTAC Headquarters Pte. Ltd. Image sensor with processor package

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Publication number Publication date
DE20109196U1 (en) 2001-09-20
GB0109826D0 (en) 2001-06-13

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