JP3502061B2 - Image sensor stack package structure - Google Patents

Image sensor stack package structure

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Publication number
JP3502061B2
JP3502061B2 JP2001153575A JP2001153575A JP3502061B2 JP 3502061 B2 JP3502061 B2 JP 3502061B2 JP 2001153575 A JP2001153575 A JP 2001153575A JP 2001153575 A JP2001153575 A JP 2001153575A JP 3502061 B2 JP3502061 B2 JP 3502061B2
Authority
JP
Japan
Prior art keywords
integrated circuit
image sensor
image
substrate
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001153575A
Other languages
Japanese (ja)
Other versions
JP2002354200A (en
Inventor
修文 杜
文銓 陳
孟南 何
立桓 陳
乃華 葉
讌程 黄
詠盛 邱
文讚 李
福洲 劉
武祥 李
孟儒 蔡
Original Assignee
勝開科技股▲ふん▼有限公司
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Publication date
Application filed by 勝開科技股▲ふん▼有限公司 filed Critical 勝開科技股▲ふん▼有限公司
Priority to JP2001153575A priority Critical patent/JP3502061B2/en
Publication of JP2002354200A publication Critical patent/JP2002354200A/en
Application granted granted Critical
Publication of JP3502061B2 publication Critical patent/JP3502061B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Transforming Light Signals Into Electric Signals (AREA)
  • Facsimile Heads (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Image Input (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明はイメージセンサのス
タックパッケージ構造に係り、特に、そのうち集積回路
及びイメージセンシングチップが異なる機能を有してパ
ッケージボデー中にパッケージされて、パッケージ基板
の数を減少でき、及び異なる機能を有する集積回路及び
イメージセンシングチップを完全にパッケージした構造
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack package structure of an image sensor, and more particularly, an integrated circuit and an image sensing chip having different functions are packaged in a package body to reduce the number of package substrates. , And a structure in which an integrated circuit having different functions and an image sensing chip are completely packaged.

【０００２】[0002]

【従来の技術】一般にセンサは信号の検出に用いられ、
それは光学或いはオーディオ信号とされうる。本発明の
センサはイメージ信号を受け取り、及びイメージ信号を
プリント基板に伝送する電気信号に変換する。2. Description of the Related Art Generally, a sensor is used for detecting a signal,
It can be an optical or audio signal. The sensor of the present invention receives an image signal and converts the image signal into an electrical signal for transmission to a printed circuit board.

【０００３】一般にイメージセンサはイメージ信号を受
け取りイメージ信号をプリント基板に伝送する電気信号
に変換する。イメージセンサはそれから電気的に他の集
積回路に接続されて必要な機能を有する。例えば、イメ
ージセンサはイメージセンサの発生した信号を処理する
ディジタル信号プロセッサに電気的に連接される。さら
に、イメージセンサはまた、マイクロコントローラ、中
央処理装置、或いはその他の回路に接続されて、必要な
機能を有する。Generally, an image sensor receives an image signal and converts the image signal into an electric signal to be transmitted to a printed circuit board. Image sensor having the necessary functionality is connected from it to the electrically other integrated circuits. For example, the image sensor is electrically coupled to a digital signal processor that processes the signal generated by the image sensor. In addition, the image sensor also has the necessary functionality connected to a microcontroller, central processing unit, or other circuitry.

【０００４】しかし、伝統的なイメージセンサはパッケ
ージされ、イメージセンサに対応する集積回路はイメー
ジセンサとは別にパッケージされる必要がある。そし
て、パッケージされたイメージセンサ及び各種の信号処
理ユニットは電気的にプリント基板に接続される。その
後、イメージセンサが電気的に信号処理ユニットに、複
数の配線によりそれぞれ接続される。ゆえに、個別に各
信号処理ユニットとイメージセンサをパッケージするた
めには、複数の基板とパッケージボデーを使用する必要
があり、このため製造コストが増した。さらに、プリン
ト基板の必要エリアは各信号処理ユニットをプリント基
板上に取り付ける時に信号処理ユニットより大きくなけ
ればならず、このため製品を小型化、薄型化、及び軽量
化することができなかった。However, the traditional image sensor is packaged, and the integrated circuit corresponding to the image sensor needs to be packaged separately from the image sensor. Then, the packaged image sensor and various signal processing units are electrically connected to the printed circuit board. Thereafter, the image sensor is the electrical signal processing unit, are connected by a plurality of wires. Therefore, in order to individually package each signal processing unit and the image sensor, it is necessary to use a plurality of substrates and a package body, which increases the manufacturing cost. Further, the required area of the printed circuit board must be larger than the signal processing unit when each signal processing unit is mounted on the printed circuit board, and thus the product cannot be made smaller, thinner and lighter.

【０００５】上述の問題を解決するため、本発明ではイ
メージセンサのスタックパッケージ構造を提供して従来
のイメージセンサによりもたらされる欠点を解決する。In order to solve the above-mentioned problems, the present invention provides a stack package structure of an image sensor to solve the drawbacks provided by the conventional image sensor.

【０００６】[0006]

【発明が解決しようとする課題】ゆえに、本発明の主要
な目的は、イメージセンサのスタックパッケージ構造を
提供し、パッケージ素子の数とパッケージコストを減少
することにある。SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a stack package structure of an image sensor, and reduce the number of package elements and the package cost.

【０００７】本発明の別の目的は、イメージセンサのス
タックパッケージ構造を提供し、製造プロセスを簡素化
及び容易とすることにある。Another object of the present invention is to provide a stack package structure of an image sensor, which simplifies and facilitates the manufacturing process.

【０００８】本発明のさらに別の目的は、イメージセン
サのスタックパッケージ構造を提供し、イメージセンシ
ング製品のエリアを減少することにある。Yet another object of the present invention is to provide a stack package structure of an image sensor and reduce the area of the image sensing product.

【０００９】本発明のさらにまた別の目的は、イメージ
センサのスタックパッケージ構造を提供し、イメージセ
ンシング製品のパッケージコスト及び試験コストを減少
することにある。Yet another object of the present invention is to provide a stack package structure of an image sensor, and reduce the package cost and test cost of an image sensing product.

【００１０】[0010]

【課題を解決するための手段】請求項１の発明は、イメ
ージセンサをプリント基板に電気的に接続するスタック
パッケージ構造において、基板と、集積回路と、イメー
ジセンシングチップと、透明層とを具え、該基板は第１
表面と該第１表面と反対に位置する第２表面を具え、該
第１表面に信号入力端子が形成され、該第２表面にプリ
ント基板に電気的に接続する信号出力端子が形成され
た、該集積回路は該基板の第１表面上に設置されて基板
の信号入力端子に電気的に接続され、該イメージセンシ
ングチップは該集積回路の上方に配置されて該集積回路
と共にスタック構造を形成し、該基板の信号入力端子に
電気的に接続され、該透明層は、逆Ｕ形状の透明樹脂体
とされ、該基板の第１表面に固定される支持柱を具え、
該透明層は該イメージセンシングチップを被覆し、該イ
メージセンシングチップに該透明層を介してイメージ信
号を受け取らせ、基板に伝送する電気信号に変換させる
ことをを特徴とする、イメージセンサのスタックパッケ
ージ構造としている。請求項２の発明は、前記集積回路
が信号処理ユニットとされたことを特徴とする、請求項
１に記載のイメージセンサのスタックパッケージ構造と
している。請求項３の発明は、前記イメージセンサのス
タックパッケージ構造において、投射層が基板の第１表
面の周囲に配置され、透明層が投射層の上に配置された
ことを特徴とする、請求項１に記載のイメージセンサの
スタックパッケージ構造としている。請求項４の発明
は、前記透明層が透明接着剤とされたことを特徴とす
る、請求項１に記載のイメージセンサのスタックパッケ
ージ構造としている。The invention according to claim 1 is an image
Stack that electrically connects the image sensor to the printed circuit board
In the package structure, the substrate, integrated circuit, and image
A sensing chip and a transparent layer, wherein the substrate is a first
A surface and a second surface opposite the first surface;
A signal input terminal is formed on the first surface, and a signal input terminal is formed on the second surface.
A signal output terminal that is electrically connected to the
And the integrated circuit is mounted on the first surface of the substrate
Is electrically connected to the signal input terminal of the
A coupling chip is disposed above the integrated circuit and the integrated circuit is
Form a stack structure together with the signal input terminal of the board
The transparent layer is electrically connected and the transparent layer has an inverted U shape.
And a support post fixed to the first surface of the substrate,
The transparent layer covers the image sensing chip,
An image signal is sent to the image sensing chip through the transparent layer.
Signal is received and converted into an electric signal to be transmitted to the board.
Image sensor stack package
Page structure. The invention of claim 2 provides a stack package structure for an image sensor according to claim 1, wherein the integrated circuit is a signal processing unit. The invention of claim 3 is characterized in that, in the stack package structure of the image sensor, the projection layer is arranged around the first surface of the substrate, and the transparent layer is arranged on the projection layer. The stack package structure of the image sensor described in 1. According to a fourth aspect of the invention, the stack package structure of the image sensor according to the first aspect is characterized in that the transparent layer is a transparent adhesive.

【００１１】[0011]

【発明の実施の形態】本発明によると、プリント基板に
電気的に接続するためのイメージセンサのスタックパッ
ケージ構造は、基板と、集積回路と、イメージセンシン
グチップと、透明層を有する。該基板は第１表面と第１
表面と反対の第２表面を有する。第１表面に信号入力端
子が形成される。第２表面に信号出力端子が設けられて
電気的に基板をプリント基板に接続するのに供される。
該集積回路は基板の第１表面に取り付けられて基板の信
号入力端子に電気的に接続される。該イメージセンシン
グチップは集積回路の上方に位置して集積回路とスタッ
ク構造を形成し、基板の信号入力端子との電気的連接に
供される。該透明層はイメージセンシングチップを被覆
する。該イメージセンシングチップはイメージ信号を透
明層を介して受け取り、及びイメージ信号を電気信号に
変換し、該電気信号は基板に伝送される。According to the present invention, a stack package structure of an image sensor for electrically connecting to a printed circuit board includes a substrate, an integrated circuit, an image sensing chip, and a transparent layer. The substrate has a first surface and a first surface.
It has a second surface opposite the surface. A signal input terminal is formed on the first surface. A signal output terminal is provided on the second surface and serves to electrically connect the board to the printed board.
The integrated circuit is mounted on the first surface of the substrate and electrically connected to the signal input terminals of the substrate. The image sensing chip is located above the integrated circuit to form a stack structure with the integrated circuit and is used for electrical connection with a signal input terminal of the substrate. The transparent layer covers the image sensing chip. The image sensing chip receives the image signal through the transparent layer and converts the image signal into an electric signal, and the electric signal is transmitted to the substrate.

【００１２】こうして、イメージセンシング製品のイメ
ージセンシングチップと集積回路が一体にパッケージさ
れる。Thus, the image sensing chip of the image sensing product and the integrated circuit are integrally packaged.

【００１３】[0013]

【実施例】図１に示されるように、イメージセンサのス
タックパッケージ構造は、基板１０、集積回路２２、イ
メージセンシングチップ２６、投射層３４、透明層３６
を具えている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a stack package structure of an image sensor includes a substrate 10, an integrated circuit 22, an image sensing chip 26, a projection layer 34 and a transparent layer 36.
It is equipped with

【００１４】基板１０は第１表面１２と第１表面１２と
反対の第２表面１４を有する。第１表面１２に信号入力
端子１６が形成される。第２表面１４に信号出力端子１
８が設けられ、該信号出力端子１８はＢＧＡ形式に配置
された金属ボールとされて、電気的に基板１０をプリン
ト基板２０に接続するのに供される。こうして基板１０
からの信号はプリント基板２０に伝送される。The substrate 10 has a first surface 12 and a second surface 14 opposite the first surface 12. The signal input terminal 16 is formed on the first surface 12. Signal output terminal 1 on the second surface 14
8 is provided, and the signal output terminal 18 is a metal ball arranged in a BGA format, and is used to electrically connect the board 10 to the printed board 20. Thus the substrate 10
Signal is transmitted to the printed circuit board 20.

【００１５】集積回路２２はディジタル信号プロセッ
サ、マイクロプロセッサ、ＣＰＵ或いはそれに類似の信
号処理ユニットとされる。集積回路２２は基板１０の第
１表面１２上に配置され、ワイヤボンディング方式で基
板１０の信号入力端子１６に電気的に接続される。こう
して、集積回路２２は基板１０に電気的に接続されて信
号を集積回路２２から基板１０に伝送する。The integrated circuit 22 is a digital signal processor, a microprocessor, a CPU or a signal processing unit similar thereto. The integrated circuit 22 is disposed on the first surface 12 of the substrate 10 and electrically connected to the signal input terminal 16 of the substrate 10 by a wire bonding method. Thus, the integrated circuit 22 is electrically connected to the substrate 10 to transmit signals from the integrated circuit 22 to the substrate 10.

【００１６】イメージセンシングチップ２６は集積回路
２２の上方に配置されて集積回路２２と共にスタック構
造を形成する。集積回路２２の上方に位置する金属ワイ
ヤ２４がイメージセンシングチップ２６に圧迫されるの
を防止するため、スペーサ２８が集積回路２２とイメー
ジセンシングチップ２６の間に配置されてそれらの間に
ギャップ３０を形成している。こうして金属ワイヤ２４
の一部がギャップ３０内に配置される。イメージセンシ
ングチップ２６は基板１０の信号入力端子１６に金属ワ
イヤ３２で電気的に接続される。こうして、イメージセ
ンシングチップ２６が基板１０に電気的に接続され、イ
メージセンシングチップ２６からの信号が基板１０に伝
送される。もし集積回路２２がディジタル信号プロセッ
サであるなら、イメージセンシングチップ２６からの信
号は前もって処理されそれからプリント基板２０に伝送
される。The image sensing chip 26 is disposed above the integrated circuit 22 and forms a stack structure with the integrated circuit 22. To prevent the metal wire 24 located above the integrated circuit 22 from being pressed against the image sensing chip 26, a spacer 28 is disposed between the integrated circuit 22 and the image sensing chip 26 and a gap 30 is provided therebetween. Is forming. Thus the metal wire 24
Is disposed in the gap 30. The image sensing chip 26 is electrically connected to the signal input terminal 16 of the substrate 10 by the metal wire 32. In this way, the image sensing chip 26 is electrically connected to the substrate 10, and the signal from the image sensing chip 26 is transmitted to the substrate 10. If the integrated circuit 22 is a digital signal processor, the signals from the image sensing chip 26 are pre-processed and then transmitted to the printed circuit board 20.

【００１７】投射層３４は基板１０の第１表面１２に位
置するフレーム構造とされ、集積回路２２とイメージセ
ンシングチップ２６を包囲する。The projection layer 34 has a frame structure located on the first surface 12 of the substrate 10 and surrounds the integrated circuit 22 and the image sensing chip 26.

【００１８】透明層３６は投射層３４を被覆する透明ガ
ラスとされてイメージセンシングチップ２６と集積回路
２２をシールする。イメージセンシングチップ２６は透
明層３６を介してイメージ信号を受け取り、該イメージ
信号を基板１０に送られる電気信号に変換する。The transparent layer 36 is made of transparent glass which covers the projection layer 34 and seals the image sensing chip 26 and the integrated circuit 22. The image sensing chip 26 receives the image signal through the transparent layer 36 and converts the image signal into an electric signal sent to the substrate 10.

【００１９】図２を参照すると、集積回路２２は導電金
属３８と共に形成され、該導電金属３８は基板１０の信
号入力端子１６にフリップチップボンディングにより電
気的に接続される。こうして集積回路２２が基板１０に
電気的に接続される。イメージセンシングチップ２６は
ワイヤボンディング方式により、基板１０の信号入力端
子１６に金属ワイヤ３２を介して電気的に接続される。Referring to FIG. 2, the integrated circuit 22 is formed with a conductive metal 38, and the conductive metal 38 is electrically connected to the signal input terminal 16 of the substrate 10 by flip chip bonding. In this way, the integrated circuit 22 is electrically connected to the substrate 10. The image sensing chip 26 is electrically connected to the signal input terminal 16 of the substrate 10 via the metal wire 32 by a wire bonding method.

【００２０】図３を参照すると、透明層３６は透明接着
剤４０とされる。イメージセンシングチップ２６が集積
回路２２の上方にスタックされ、イメージセンシングチ
ップ２６と集積回路２２が電気的に基板１０に接続され
た後、透明接着剤４０でイメージセンシングチップ２６
と集積回路２２が被覆される。こうしてイメージセンシ
ングチップ２６が透明接着剤４０を介してイメージ信号
を受け取り、イメージ信号を基板１０に伝送される電気
信号に変換する。該電気信号はそれから集積回路２２に
より処理される。Referring to FIG. 3, the transparent layer 36 is a transparent adhesive 40. After the image sensing chip 26 is stacked above the integrated circuit 22 and the image sensing chip 26 and the integrated circuit 22 are electrically connected to the substrate 10, the image sensing chip 26 is bonded with the transparent adhesive 40.
And the integrated circuit 22 is covered. Thus, the image sensing chip 26 receives the image signal via the transparent adhesive 40 and converts the image signal into an electric signal transmitted to the substrate 10. The electrical signal is then processed by integrated circuit 22.

【００２１】図４を参照すると、透明層は基板１０の第
１表面１２上に配置された支持柱４２を具えた逆Ｕ形透
明層３６とされる。該逆Ｕ形透明接着剤４０は射出成形
或いは加圧成形により形成される。集積回路２２が基板
１０にフリップチップボンディングにより電気的に接続
された後、イメージセンシングチップ２６が集積回路２
２の上方にスタックされる。それからイメージセンシン
グチップ２６が基板１０に、ワイヤボンディングにより
金属ワイヤ３２を介して電気的に接続される。その後、
逆Ｕ形の透明接着剤４０が直接基板１０の第１表面１２
に設けられ、イメージセンシングチップ２６と集積回路
２２をシールする。イメージセンシングチップ２６は逆
Ｕ形の透明接着剤４０を介してイメージ信号を受け取
り、基板１０に伝送される電気信号に変換する。Referring to FIG. 4, the transparent layer is an inverted U-shaped transparent layer 36 having support posts 42 disposed on the first surface 12 of the substrate 10. The inverted U-shaped transparent adhesive 40 is formed by injection molding or pressure molding. After the integrated circuit 22 is electrically connected to the substrate 10 by flip-chip bonding, the image sensing chip 26 is connected to the integrated circuit 2.
Stacked above 2. Then, the image sensing chip 26 is electrically connected to the substrate 10 by wire bonding via the metal wire 32. afterwards,
The inverted U-shaped transparent adhesive 40 is directly attached to the first surface 12 of the substrate 10.
And seals the image sensing chip 26 and the integrated circuit 22. The image sensing chip 26 receives the image signal through the inverted U-shaped transparent adhesive 40 and converts the image signal into an electric signal transmitted to the substrate 10.

【００２２】[0022]

【発明の効果】以上により、本発明は以下のような優れ
た点を有する。 １．イメージセンシングチップ２６と集積回路２２が一
体にパッケージされているため、基板１０形成材料を減
らすことができ、ゆえにイメージセンシング製品の製造
コストを削減できる。 ２．イメージセンシングチップ２６と集積回路２２が一
体にパッケージされているため、イメージセンシング製
品の区域を減少できる。 ３．イメージセンシングチップ２６と集積回路２２が一
体にパッケージされているため、ただ一つのパッケージ
ボデーしかない。ゆえにただ一つの試験設備しか使用す
る必要がなく、試験コストも減少できる。 ４．イメージセンシングチップ２６と集積回路２２が一
体にパッケージされているため、二つのチップがたった
一つのパッケージプロセスによりパッケージされる。ゆ
えにパッケージコストを有効に減少できる。As described above, the present invention has the following excellent points. 1. Since the image sensing chip 26 and the integrated circuit 22 are integrally packaged, the material for forming the substrate 10 can be reduced and therefore the manufacturing cost of the image sensing product can be reduced. 2. Since the image sensing chip 26 and the integrated circuit 22 are integrally packaged, the area of the image sensing product can be reduced. 3. Since the image sensing chip 26 and the integrated circuit 22 are integrally packaged, there is only one package body. Therefore, only one test facility needs to be used and the test cost can be reduced. 4. Since the image sensing chip 26 and the integrated circuit 22 are integrally packaged, the two chips are packaged by only one packaging process. Therefore, the package cost can be effectively reduced.

【００２３】以上の説明は本発明の実施例に係るもので
あり、本発明の請求範囲を限定するものではなく、本発
明に基づきなしうる細部の修飾或いは改変は、いずれも
本発明の請求範囲に属するものとする。The above description relates to the embodiments of the present invention, and is not intended to limit the scope of the claims of the present invention, and any modifications or alterations in details that can be made based on the present invention are claimed in the scope of the present invention. Shall belong to.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１実施例によるイメージセンサのス
タックパッケージ構造表示図である。FIG. 1 is a view showing a stack package structure of an image sensor according to a first embodiment of the present invention.

【図２】本発明の第２実施例によるイメージセンサのス
タックパッケージ構造表示図である。FIG. 2 is a view showing a stack package structure of an image sensor according to a second embodiment of the present invention.

【図３】本発明の第３実施例によるイメージセンサのス
タックパッケージ構造表示図である。FIG. 3 is a view showing a stack package structure of an image sensor according to a third embodiment of the present invention.

【図４】本発明の第４実施例によるイメージセンサのス
タックパッケージ構造表示図である。FIG. 4 is a view showing a stack package structure of an image sensor according to a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０ 基板 ２２ 集積回路 ２６ イメージセンシングチップ ３４ 投射層 ３６ 透明層 １２ 第１表面 １４ 第２表面 １６ 信号入力端子 １８ 信号出力端子 ２０ プリント基板 ２４ 金属ワイヤ ２８ スペーサ ３０ ギャップ ３８ 導電金属 ３２ 金属ワイヤ ４０ 透明接着剤 10 substrates 22 integrated circuits 26 Image Sensing Chip 34 Projection layer 36 transparent layer 12 First surface 14 Second surface 16 signal input terminals 18 signal output terminal 20 printed circuit boards 24 metal wire 28 Spacer 30 gap 38 Conductive metal 32 metal wire 40 transparent adhesive

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０４Ｎ 5/335 Ｈ０１Ｌ 31/02 Ｂ (72)発明者 黄 讌程 台湾新竹縣竹北市泰和路84號 (72)発明者 邱 詠盛 台湾新竹縣竹北市泰和路84號 (72)発明者 李 文讚 台湾新竹縣竹北市泰和路84號 (72)発明者 劉 福洲 台湾新竹縣竹北市泰和路84號 (72)発明者 李 武祥 台湾新竹縣竹北市泰和路84號 (72)発明者 蔡 孟儒 台湾新竹縣竹北市泰和路84號 (56)参考文献 特開 平１−184865（ＪＰ，Ａ) 特開 平２−146759（ＪＰ，Ａ) 特開 昭61−214565（ＪＰ，Ａ) 特開 平５−343655（ＪＰ，Ａ) 特開 平７−23173（ＪＰ，Ａ) 特開 昭63−129774（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H04N 1/024 - 1/036 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 7 Identification symbol FI H04N 5/335 H01L 31/02 B (72) Inventor Huang Yan-Shang, Hsinchu, Taiwan 84 Taiwa Road, Taibei City (72) Inventor, Egu Wang Sheng, Hsinchu County, Taiwan 84, Taihe Road, Taibei City, 72 (72) Inventor, Li Wen-San, Hsinchu County, Taiwan 84, Taihe Road, Taihoku, Taiwan (72) Inventor, Liu Fuzhou, Taiwan 84, Taihe Road, Taibe Road, Taiwan (72) Lee Wusho Taiwan 84, Taihe Road, Bamboo City, Taiwan (72) Inventor Cai Meng, Taiwan 84, Taihe Road, Bamboo City, Taiwan (56) Reference JP 1-184865 (JP, A) JP 2-146759 (JP, A) JP 61-214565 (JP, A) JP 5-343655 (JP, A) JP 7-23173 (JP, A) JP 63-129774 (JP, A) (JP 58) Fields surveyed (Int.Cl. 7 , DB name) H04N 1/024-1/036

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 イメージセンサをプリント基板に電気的
に接続するスタックパッケージ構造において、基板と、
集積回路と、イメージセンシングチップと、透明層とを
具え、 該基板は第１表面と該第１表面と反対に位置する第２表
面を具え、該第１表面に信号入力端子が形成され、該第
２表面にプリント基板に電気的に接続する信号出力端子
が形成された、 該集積回路は該基板の第１表面上に設置されて基板の信
号入力端子に電気的に接続され、 該イメージセンシングチップは該集積回路の上方に配置
されて該集積回路と共にスタック構造を形成し、該基板
の信号入力端子に電気的に接続され、 該透明層は、逆Ｕ形状の透明樹脂体とされ、該基板の第
１表面に固定される支持柱を具え、該透明層は該イメー
ジセンシングチップを被覆し、該イメージセンシングチ
ップに該透明層を介してイメージ信号を受け取らせ、基
板に伝送する電気信号に変換させることをを特徴とす
る、イメージセンサのスタックパッケージ構造。 1. An image sensor is electrically connected to a printed circuit board.
In the stack package structure connected to
Integrated circuit, image sensing chip, transparent layer
Comprising a first surface and a second surface located opposite the first surface.
And a signal input terminal is formed on the first surface.
2 Signal output terminals that are electrically connected to the printed circuit board on the surface
And the integrated circuit is mounted on the first surface of the substrate to form the integrated circuit.
Is electrically connected to the signal input terminal, and the image sensing chip is disposed above the integrated circuit.
To form a stack structure with the integrated circuit, the substrate
Electrically connected to the signal input terminal of the substrate, the transparent layer is an inverted U-shaped transparent resin body, and
1 a support pillar fixed to the surface, the transparent layer being the image
The image sensing chip is covered by covering the image sensing chip.
To receive an image signal through the transparent layer.
Characterized by converting into an electric signal to be transmitted to the board
Image sensor stack package structure. 【請求項２】 前記集積回路が信号処理ユニットとされ
たことを特徴とする、請求項１に記載のイメージセンサ
のスタックパッケージ構造。2. The stack package structure for an image sensor according to claim 1, wherein the integrated circuit is a signal processing unit. 【請求項３】 前記イメージセンサのスタックパッケー
ジ構造において、投射層が基板の第１表面の周囲に配置
され、透明層が投射層の上に配置されたことを特徴とす
る、請求項１に記載のイメージセンサのスタックパッケ
ージ構造。3. The stack package structure of the image sensor according to claim 1, wherein the projection layer is arranged around the first surface of the substrate, and the transparent layer is arranged on the projection layer. Image sensor stack package structure. 【請求項４】 前記透明層が透明接着剤とされたことを
特徴とする、請求項１に記載のイメージセンサのスタッ
クパッケージ構造。4. The stack package structure for an image sensor according to claim 1, wherein the transparent layer is a transparent adhesive.
JP2001153575A 2001-05-23 2001-05-23 Image sensor stack package structure Expired - Fee Related JP3502061B2 (en)

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