GB2368973A - Integrated circuit with conductive region at periphery of substrate and bond pads for measuring to detect failure - Google Patents

Integrated circuit with conductive region at periphery of substrate and bond pads for measuring to detect failure Download PDF

Info

Publication number
GB2368973A
GB2368973A GB0115078A GB0115078A GB2368973A GB 2368973 A GB2368973 A GB 2368973A GB 0115078 A GB0115078 A GB 0115078A GB 0115078 A GB0115078 A GB 0115078A GB 2368973 A GB2368973 A GB 2368973A
Authority
GB
United Kingdom
Prior art keywords
conductive
integrated circuit
bond pads
substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0115078A
Other languages
English (en)
Other versions
GB0115078D0 (en
Inventor
Vivian Wanda Ryan
Thomas Herbert Shilling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Guardian Corp filed Critical Agere Systems Guardian Corp
Publication of GB0115078D0 publication Critical patent/GB0115078D0/en
Publication of GB2368973A publication Critical patent/GB2368973A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Automation & Control Theory (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
GB0115078A 2000-06-27 2001-06-20 Integrated circuit with conductive region at periphery of substrate and bond pads for measuring to detect failure Withdrawn GB2368973A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/604,519 US6833557B1 (en) 2000-06-27 2000-06-27 Integrated circuit and a method of manufacturing an integrated circuit

Publications (2)

Publication Number Publication Date
GB0115078D0 GB0115078D0 (en) 2001-08-15
GB2368973A true GB2368973A (en) 2002-05-15

Family

ID=24419923

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0115078A Withdrawn GB2368973A (en) 2000-06-27 2001-06-20 Integrated circuit with conductive region at periphery of substrate and bond pads for measuring to detect failure

Country Status (5)

Country Link
US (1) US6833557B1 (enExample)
JP (1) JP3944764B2 (enExample)
KR (1) KR100823043B1 (enExample)
GB (1) GB2368973A (enExample)
TW (1) TW512511B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10254756A1 (de) * 2002-11-23 2004-06-09 Infineon Technologies Ag Vorrichtung und Verfahren zur Erfassung von Stressmigrations-Eigenschaften
US7888672B2 (en) 2002-11-23 2011-02-15 Infineon Technologies Ag Device for detecting stress migration properties

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4949733B2 (ja) * 2006-05-11 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置
KR100764660B1 (ko) * 2006-11-01 2007-10-08 삼성전기주식회사 주파수 종속 특성을 가지는 다중 배선의 신호 천이시뮬레이션 방법
DE102014222203B3 (de) 2014-10-30 2016-03-10 Infineon Technologies Ag Überprüfung von Randschäden
US20190250208A1 (en) * 2018-02-09 2019-08-15 Qualcomm Incorporated Apparatus and method for detecting damage to an integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6387736A (ja) * 1986-09-30 1988-04-19 Nec Corp 半導体装置
JPH02151048A (ja) * 1988-12-01 1990-06-11 Nec Corp 半導体集積回路
JPH04199651A (ja) * 1990-11-29 1992-07-20 Fujitsu Ltd 半導体装置およびその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177221A (ja) * 1992-12-07 1994-06-24 Fujitsu Ltd 信頼性評価用半導体装置及び信頼性評価用の評価パターンを内蔵した製品ｌｓｉ、ウエハー
JP3269171B2 (ja) * 1993-04-08 2002-03-25 セイコーエプソン株式会社 半導体装置およびそれを有した時計
JPH07201855A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 半導体装置
JP3270807B2 (ja) * 1995-06-29 2002-04-02 シャープ株式会社 テープキャリアパッケージ
KR100190927B1 (ko) * 1996-07-18 1999-06-01 윤종용 슬릿이 형성된 금속막을 구비한 반도체 칩 장치
JP3111938B2 (ja) * 1997-09-16 2000-11-27 日本電気株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6387736A (ja) * 1986-09-30 1988-04-19 Nec Corp 半導体装置
JPH02151048A (ja) * 1988-12-01 1990-06-11 Nec Corp 半導体集積回路
JPH04199651A (ja) * 1990-11-29 1992-07-20 Fujitsu Ltd 半導体装置およびその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10254756A1 (de) * 2002-11-23 2004-06-09 Infineon Technologies Ag Vorrichtung und Verfahren zur Erfassung von Stressmigrations-Eigenschaften
WO2004048985A1 (de) * 2002-11-23 2004-06-10 Infineon Technologies Ag Vorrichtung und verfahren zur erfassung von stressmigrations-eigenschaften
CN100554988C (zh) * 2002-11-23 2009-10-28 因芬尼昂技术股份公司 检测应力迁移性质的装置及方法
US7888672B2 (en) 2002-11-23 2011-02-15 Infineon Technologies Ag Device for detecting stress migration properties
DE10254756B4 (de) * 2002-11-23 2011-07-07 Infineon Technologies AG, 81669 Vorrichtung und Verfahren zur Erfassung von Stressmigrations-Eigenschaften
US8323991B2 (en) 2002-11-23 2012-12-04 Infineon Technologies Ag Method for detecting stress migration properties

Also Published As

Publication number Publication date
KR20020001632A (ko) 2002-01-09
US6833557B1 (en) 2004-12-21
JP2002093918A (ja) 2002-03-29
GB0115078D0 (en) 2001-08-15
KR100823043B1 (ko) 2008-04-17
JP3944764B2 (ja) 2007-07-18
TW512511B (en) 2002-12-01

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)