GB2349249A

GB2349249A - Repair circuit of a semiconductor memory device

Info

Publication number: GB2349249A
Application number: GB0000354A
Authority: GB
Inventors: Jin-Keun Oh; Phil-Jung Kim; Jae-Kyung Wee; Douk-Hyun Ryu; Young-Ho Seol; Ho-Youb Cho
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1999-01-09
Filing date: 2000-01-10
Publication date: 2000-10-25
Also published as: JP2000207896A; TW459238B; KR20000050454A; GB0000354D0; KR100510995B1

Abstract

A repair circuit of a manufactured semiconductor memory device (e.g. a DRAM) uses preinstalled alternative address lines to address a redundant cell when an address signal for an identified defective cell is selected. The repair circuit has a redundancy column address control circuit 30 (and Fig. 2) and a repair signal generator 50 electrically connected thereto and including an address input unit made up of a plurality of transistors connected in parallel (20a' and 20b', Fig. 4). An anti-fuse programming circuit 40 is provided with a plurality of anti-fuses, programmed according to test results of the memory device to generate a programming value for controlling switching fuse circuits (51a and 51b, Fig. 4) of the repair signal generator 50. Thus, defects of a package-level memory device which may occur during a burn-in test, i.e. after a laser-beam repair process has been performed to a wafer-level chip, may be repaired, to thereby reduce the chip area occupied by the repair circuit and enable repair processes to be performed at both wafer-level and package-level of the memory device.

Description

348GB 2349249 SEMICONDUCTOR MEMORY DEVICE

INTRODUCTION

The present invention relates to a repair circuit of a semiconductor memory device such as a DRAM, and more particularly to a repair circuit in which a programming value based on a plurality of programmed anti- fuses is used in lieu of polysilicon fuses cut by a laser beam.

Since a variety of factors involved throughout the fabrication of a semiconductor device affect reliability of a product, a variety of tests are performed at each step of manufacture to achieve the desired characteristics of the final semiconductor device, with slight variations in any step resulting in great variations in performance. Therefore, every fabricated semiconductor device goes through a battery of tests to confirm that each product has been manufactured as originally designed.

If even one of a large number of defined cells in a semiconductor memory device is defective in its operation, the memory device as a whole must be treated as a defective (unusable) product, because the device cannot be normally operated as a dynamic random access memory (DRAM). It is, however, highly impractical to discard the entire memory device when only a very few of the defined cells are actually defective, which is especially true as the integration of a DRAM device increases. Therefore, when defective cells are present, which is an inevitable occurrence, such cells are replaced with spare or "redundant" - memory cells. The redundant memory cells are embedded (pre-installed) within a 25 manufactured DRAM device, in the form a redundancy circuit, for the express purpose of replacing all identified defective cells and thereby improving the yield of the final product.

The adverse result of this universal provision of redundant memory cells is an undesirable increase of the area of a given chip, which in turn increases the complexity of the test for identifying the defective cells themselves, as well as an increase in current consumption.

63348GB 2 Nevertheless, such a technique of installing a redundancy circuit is generally used in 64-256Kb DRAMs as a standard practice, since the increased chip area and current consumption is not excessive. Typically, a redundancy circuit for a memory cell is preinstalled in each sub-array block, whereby spare rows and columns are established, thereby enabling the replacement of each defective cell with a redundant memory cell in a row/column when cell defects are identified.

To identify the defective memory cells, an electrical test is performed to check each memory cell of every memory device of a completed wafer. Then, the memory devices are "reprogrammed" using a repair circuit to effectively change the addresses of the defective cells, such that when the address signal for a defective cell is selected, a spare (replacement) cell is intemally addressed in its place. In doing so, when the defective addresses are input to the memory device during its actual operation, pre-installed alternative address lines are selected instead of the addresses originally corresponding to defective lines.

Such a programming method can be achieved by one of several methods, for example, by burning open a pre-installed fuse using a current overload, as an ordinary electrical fuse; using a laser beam to cut traces (polysilicon or metal interconnections) in order to create an electrical open or an electrical short; or by programming an EPROM memory cell. Among these methods, the laser cutting method is simple and precise and therefore widely used and the circuits of FIGS. I and 2 are employed in such circumstances.

After the repair is performed by a laser-beam cutting operation, the successftil repair and memory cell function is confirmed by an additional test, and then the chip is packaged to become a final product of a semiconductor device. In order to detect potential defects of the packaged semiconductor device in advance of failure, a bum-in test is performed by stressing the package-level semiconductor device using excessive voltages and extreme temperatures, which typically experiences an additional 5-15% failure rate. These defective products are no longer repairable and must be discarded or recycled.

63348GB 3 In order to solve the aforementioned problem, instead of programmed polysilicon fuses, which occupy a very large layout area, anti-fuses can be used in addition to the polysilicon fuses, thereby easily performing a repair process to a package-level semiconductor device. The construction of a repair circuit with only anti-fuses, however, requires a high-voltage programming circuit for breaking down the insulating layer of the anti- fuses which increases the occupying area of the repair circuit, thereby increasing the size of the final product.

Therefore, it is an object of the present invention to provide an improved repair circuit of a semiconductor device, which solves one or more of the aforementioned problems of the conventional art.

In one aspect, the present invention aims to provide a repair circuit of a semiconductor device, which enables a package level repair of the manufactured semiconductor device, using an electrical repair method as a secondary repair process for such defects as may be generated during burnin testing.

In another aspect, the present invention aims to provide a repair circuit of a semiconductor device, which enables a reduction in the chip area occupied by the repair circuit.

The invention provides a repair circuit of a semiconductor memory device, having a redundancy column address control circuit and a repair signal generator electrically connected to the redundancy column address control circuit, the repair signal generator including an address input unit made up of a plurality of transistors connected in parallel. The repair circuit comprises an anti-fuse programming circuit provided with a plurality of anti-fuses, the anti-fuses being programmed according to test results of the semiconductor memory device to generate a programming value representing the state of the plurality of 63348GB 4 anti-fuses. Characteristically, the repair signal generator includes a switching fuse part controlled according to the programming value.

Therefore, a repair step for defective cells can be performed to a processed chip at wafer level by cutting polysilicon fuses of the conventional repair circuit with a laser beam, but another repair step can be performed to the manufactured semiconductor device at package level, for defects occurring in a bum-in test or the like, by programming anti-fuses in order to generate a programming value for controlling the switching fuse circuits of the repair signal generator, consequently decreasing the area occupied by the repair circuit. Thus, defects of a package-level memory device which may occur during a bum-in test, i.e. after a laser-beam repair process has been performed to a wafer-level chip, may be repaired, to thereby reduce the chip area occupied by the repair circuit and enable repair processes to be performed at both wafer-level and package-level of a semiconductor memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described in detail with reference to the accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification in order to illustrate embodiments of the invention, and which, together with the following detailed description, serve to explain the principles of the invention. In the drawings:

FIG. I is a block diagram of a repair circuit of a semiconductor device in accordance with the present invention; FIG. 2 a circuit diagram of a redundancy column address control circuit of a contemporary semiconductor device; 63348GB FIG. 3 is a circuit diagram of a conventional laser-type repair circuit of a contemporary semiconductor device; FIG. 4 is a circuit diagram of the repair signal generator shown in FIG. 1; and 5 FIG. 5 is a timing diagram illustrating the operation of the repair signal generator of FIG. 4.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Referring to FIG. 1, a repair circuit of a semiconductor device in accordance with the present invention comprises a redundancy column address control circuit 30, a plurality of anti-fuse programming circuits 40, and a repair signal generator 50. Any one of the anti- fuse programming circuits 40 may be comprised of a circuit as substantially described in either of two U.S. patent applications and corresponding to Korean applications No. 98-62537 and No. 99-346, recently filed by this applicant.

Referring to the circuit diagram of FIG. 2, showing the redundancy column address control circuit 30 of a contemporary semiconductor device, a row address strobe (RAS) active signal and global row and column address signals are input to generate output signals, in the form of row and column pre-charge signals and a spare enable signal. The RAS active signal is used for turning on a transmission gate T32, which is enabled by a low level pulse - when a bank "0" (for example, a 64Mb DRAM has four banks: 130-133) is active low. Then, 25 either one of the global row address signals is enabled high, to pass through the transmission gate T32, so that the spare enable output signal is enabled low. As soon as the global row address signal is disabled low, the spare enable output signal is enabled low. The width of the pulse is determined by five inverters 3 1.

63348GB 6 Whenever an address is input, regardless of whether the address has internal (decoded) or external (general accessing) origins, the global column address signal is enabled high. As soon as the global column address signal is disabled low, the column pre-charge signal is enabled low.

FIG. 3 is a circuit diagram of the repair signal generator of a conventional repair circuit of a semiconductor device, in which a lasercutting technique is employed, utilising polysilicon fuses. As shown in FIG. 3, a polysilicon fuse part 1 Oa is connected in series with an address input unit 20a, and a pair of polysilicon fuse parts I Oa and I Ob is connected in series with an address input unit 20b. A repair operation is performed based on a SPARE signal according to the cutting (or non-cutting) of the polysilicon fuses with respect to an input address through the address input units 20a and 20b.

A row pre-charge signal is initially high, while a refresh signal, for inducing the refresh mode, is low (inactive). In this state, with the decoded row address lines held low, a node Ila" is pre-charged to a high level. Thus, the spare enable output signal is high, so that a normal mode reset signal is also high. With the normal mode rest signal in this state (high) and a column pre-charge signal also at a high level, the decoded column address signals are held low, i.e., in the pre-charge state, such that a node "b" is pre-charged high. If a column address is input, either internally or externally, a column load reduction signal is enabled high. Accordingly, the SPARE signal is disabled high.

In the normal operation of such a repair circuit, in which a pre-charge condition has been initiated as above, if any of the row addresses go high, one block of memory (e.g., IMb) among several (e.g., eight) such blocks units is selected. Then, the pre- charged node "a" is discharged to a low level, and spare enable output signal is disabled low with the inputs of a low level pulse of the RAS active signal and a high level pulse of the global row address signal, to turn on a transmission gate T52. At this time, the non-nal mode reset signal stays high. Therefore, pre-charged node "b" is discharged to a low level if any of the column 63348GB 7 address signals, or the column load reduction signal, goes high, at which time the SPARE signal is disabled high so that a repair is not performed, thereby allowing normal cell access.

However, should the polysilicon fuse of a predetermined address, i.e., a defective address, be cut by laser beam in process of performing a repair to that address. For instance, if any of the polysilicon fuses are cut, three row address lines are used for selecting one out of eight IMb blocks, while, seven column address lines are used for selecting one out of 128 signals from a colurrin decoder.

As mentioned above, initially, the row pre-charge signal is high and the refresh signal is low. Also, a decoded row address line is enabled high, but the corresponding polysilicon fuses are cut. As a result, node "a" is continuously pre-charged to a high level. With a low level pulse of the RAS active signal, the spare enable output signal disables the transmission gate T52, so that the normal mode reset signal is disabled low. Therefore, with the normal mode reset signal at a low level, the column pre-charge signal goes high. Similarly, a decoded column address signal is initially enabled high, but, with the polysilicon fuse cut, node "b" is not discharged and is kept at a high level. Accordingly, the SPARE signal goes low, thereby allowing a redundancy column to be enabled.

A repair circuit employing such a conventional repair signal generator, however, exhibits the drawbacks as described above. Thus, in order to achieve the objects of the present invention, the circuit of FIG. 4 is utilised in its stead.

FIG. 4 specifically shows that part of the circuit involving the repair process to be performed on a manufactured semiconductor device at the package level, i. e., after completing the bum-in test to the wafer-level chip, in which first and second switching fuse parts 5 1 a and 5 1 b are employed instead of the polysilicon fuse parts of FIG. 3. The first and second switching fuse parts 51a and 51b are made of a plurality of NMOS transistors switched according to an electric potential, high or low, of a programming value output from the anti-fuse programming circuits 40, comprised of 22 like circuits, in response to a 63348GB r ' '), program state of the 22 anti-fuses included therein. The NMOS transistors of the switching fuse circuits 5 1 a and 5 1 b are turned on/off by programming the anti-fuses in the packagelevel semiconductor device, after the burn-in test, to thereby perform a secondary repair for an address relevant to defective cells to be input through address input parts 20a' and 20b'.

Even though the preferred embodiment shown in FIG. 4 employs NMOS transistors for the switching fuse parts 51a and 51b, PMOS transistors may be used in their stead with the same results. The substrates of the NMOS transistors, or such PMOS transistors, are grounded.

Referring to the timing diagram of FIG. 5, in the operation of the repair circuit of the present invention, the programming value is latched according to whether the corresponding antifuse is programmed. That is, if an anti-fuse is programmed, its programming value signal is latched low, and the programming value is latched high for anti-fuses not programmed.

Accordingly, with no anti-fuse programmed, the same state of signals are kept as in the case in which polysilicon fuses are employed using the circuit of FIG. 3.

In contrast to the circuit described with respect to FIG. 3, instead of decoded row and column signals, the repair circuit of the present invention utilises a programming value to control the NMOS transistors of the switching fuse parts 5 1 a and 5 1 b. That is, during the normal operation of the pre-charged repair circuit, with the row pre-charge signal high and the refresh signal low, a decoded row address is enabled high. In this state, the anti-fuses of the anti- fuse programming circuits 40 are programmed so that the programming value line goes low to turn off the corresponding NMO S transistor of the first switching fuse part 5 1 a.

Similarly, with the normal mode reset signal is disabled (low) and the column pre-charge signal high, the anti-fuses of the anti-fuse programming circuits 40 are programmed so that the programming value line goes low, to turn off the corresponding NMOS transistor of the second switching fuse part 5 1 b.

63348GB 9 Therefore, according to the repair circuit of a semiconductor device of the present invention, a package level repair of the semiconductor device is enabled by utilising a programming value to control the operation of an electrical repair method as a secondary repair process for such defects as may be generated during bum-in testing. In addition, a reduction in the chip area occupied by the repair circuit is enabled by the use of anti- fuses instead of polysilicon fuses to be cut by a laser beam.

Since the present invention may be embodied in various forms, without departing from the essential characteristics thereof, it should be understood that the above-described embodiment is not to be limited by any of the details of the foregoing description, unless otherwise specified, but should be construed only as defined in the appended claims. Thus, all modifications that fall within the scope of the claims are therefore intended to be embraced thereby.

63348GB

Claims

1. A repair circui f a semiconductor memory device, having a redundancy column address control circuit and a repair signal generator electrically connected to said redundancy column address control circuit, said repair signal generator including an address input unit made up of a plurality of transistors connected in parallel, said repair circuit comprising:

an anti-fuse programming circuit provided with a plurality of anti-fuses, said anti-fuses being programmed according to test results of the semiconductor memory device to generate a programming value representing the state of said plurality of anti-fuses, wherein said repair signal generator includes a switching fuse part controlled according to said programming value.

2. The repair circuit as claimed in claim 1, wherein said switching fuse part is made up of a plurality of transistors connected in series with the transistors of said address unit.

3. The repair circuit as claimed in claim 2, wherein said plurality of transistors connected in series with the transistors of said address unit are NMOS transistors whose substrate are at ground potential.

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4. A semiconductor memory device provided with a repair circuit substantially as described herein with reference to Figures 1, 2, 4 and 5 of the accompanying drawings.

5. A semiconductor memory device as claimed in any of claims I to 4, the device being part of a wafer containing a number of similar devices.

63348GB

6. A semiconductor device as claimed in any of claims I to 4, the device having been packaged and repaired separately from other devices with which it was fabricated as part of a larger wafer.

7. A process for manufacture of a semiconductor device, the process including fabricating said device together with similar devices on a semiconductor wafer, testing and repairing the device while on the wafer, separating the device from the wafer and packaging the device, wherein the semiconductor device incorporates a repair circuit which enables a package level repair of the manufactured semiconductor device, the process further including using an electrical repair method as a secondary repair process.

8. A process as claimed in claim 4 wherein said secondary repair process is applied to repair defects generated during bum-in testing of the packaged device.

9. A process of manufacturing a packaged semiconductor memory device substantially as described herein with reference to Figures 1, 2, 4 and 5 of the accompanying drawings.