KR100434319B1 - Circuit for Repairing Fail in Semiconductor Memory Device - Google Patents

Abstract

The present invention performs repair after packaging using an anti-fuse unit, and configures a circuit for controlling the anti-fuse unit to perform the repair. In this case, an address signal is applied to a fuse set provided by the number of word lines. A comparator for comparing a hit of each fuse set and outputting a heat comparison signal, and disabling the normal word line in which a fail occurs by performing a heat island processing by receiving the heat comparison signal and replacing the normal word line. To replace the redundant word line or normal word line, which failed after packaging, to the repair circuit of the semiconductor device configured as a word line controller to enable the redundant word line, the address signal is applied to drive the anti-fuse set program to each address. Anti-redundant by checking for star hits and treating them with heat islands Characterized in that it further comprises an anti-enable to enable the word line.

Description

Circuit for Repairing Fail in Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, to perform repair after packaging using an anti-fuse part and to perform a repair by configuring a circuit for controlling the anti-fuse part, a single bit fail The present invention relates to a repair circuit of a semiconductor memory device which repairs not only a bit fail but also a word line fail.

In general, a repair circuit of a semiconductor memory element refers to a circuit in a semiconductor memory element which performs a task of replacing a spare cell (repair cell) included in the element in order to remedy a defect of a minute memory cell.

Spare cells of semiconductor memory devices are installed in sub-array blocks. Spare rows and spare columns are pre-installed in each cell array to replace defective memory cells with row / column spare memory cells. Is used.

When the wafer process step is completed, the internal circuit is programmed to select a defective memory cell through a test and replace the corresponding address with the address signal of the spare cell. Thus, the address corresponding to the defective line in actual use is performed. Is entered, the selection will switch to the spare line instead.

Such a program method includes an electric fuse method that melts and blows a fuse due to overcurrent, a method of burning a fuse with a laser beam, a method of shorting a junction with a laser beam, and an EPROM. Programming with memory cells.

Among the programming methods, a short-junction method using a laser beam has been preferred at the wafer level. However, an electrical programming method has recently been used to test a device after packaging.

In particular, in an electrically programmable memory device, such an electrical programming method can result in a significant yield improvement by repairing multiple patterns of fail after packaging.

The above-described failing packaging may be repaired by additionally configuring an anti fuse.

In general, an anti-fuse is a reverse concept of a fuse and is set to an "OFF" state at the beginning of fabrication of a semiconductor memory device, and then switched to an "ON" state by a program after packaging.

In other words, the anti-fuse in the early stage of manufacture is in the state of an insulator having an electrical resistance of several MΩ or more and then converted into a conductor having an electrical resistance of several hundred Ω or less by a program.

When the anti-fuse is programmed, the physical change of the anti-fuse causes an insulator to breakdown by applying a voltage above a certain level between two electrodes, that is, between the first conductive layer and the second conductive layer. It is made to be converted into a conductor.

Since the magnitude of the programming voltage is generally greater than the normal operating voltage, the programming voltage can impair and reduce the reliability of the associated adjacent elements and inappropriately separated peripheral circuits. In particular, the peripheral circuitry for providing the programming voltage and reading the anti-fuse resistance is generally attached directly to the anti-fuse element, which may cause potential damage.

Hereinafter, a repair circuit of a conventional semiconductor memory device having an anti-fuse will be described with reference to the accompanying drawings.

1 is a block diagram showing a repair circuit of a conventional semiconductor memory device having an anti fuse.

As shown in FIG. 1, a conventional repair circuit includes a spare column decoder configured to receive a column address signal and output a selection signal, a memory block driven by the selection signal of the spare column decoder, Comprising an operation unit for applying a control signal to the memory block by receiving the signal of the column decoder, and an anti-fuse block for replacing the fuse generated by the output of the memory block and the column address signal with anti-fuse and driving the anti-cell do.

Since a signal is applied from a spare column decoder that is selectively applied for each memory block, the conventional repair circuit can repair only a single bit fail.

The operation of the repair circuit of the conventional semiconductor memory element is as follows.

If a 1-bit fail occurs during packaging, input the same address as the fail cell in the anti-fuse circuit to prevent data to be read / written to the fail cell. Read / write to an anti-cell instead.

In other words, when anti-fuse driving and row and column addresses are designated after the anti-fuse operation, the address is recognized by the original cell and the anti-fuse block at the same time, so that an address path applied to the fail cell (fail cell0) is lost. The disable, and the address path applied to the anti cell is enabled to perform the repair.

However, the repair circuit of the conventional semiconductor memory device as described above has the following problems.

First, in the packaging state, only a single bit fail can be repaired, and when the fail bit increases, the number of anti-fuse increases as much as the fail bit increases, thereby occupying a large area in the memory device, thereby reducing the integration of the semiconductor device.

Second, after packaging, only a single bit fail can be repaired, so when an error occurs on a word line or when data line failure occurs, only an anti fuse is used. Repair is not possible with the conventional circuit provided, and a new repair circuit is required.

The present invention has been made to solve the above problems, and after repairing by using an anti-fuse unit (anti fuse) to perform a repair, and in the process of repairing by configuring a circuit for controlling the anti-fuse unit, a single bit It is an object of the present invention to provide a repair circuit of a semiconductor memory device that repairs not only a single bit fail but also a word line fail.

1 is a block diagram showing a repair circuit of a conventional semiconductor memory device.

Fig. 2 is a block diagram showing a repair circuit of a semiconductor memory device as a first embodiment of the present invention.

3 is a block diagram showing a repair circuit of a semiconductor memory device according to a second embodiment of the present invention.

4 is a circuit diagram illustrating an anti-fuse programming unit of FIG. 2 or 3.

5 is a timing diagram showing signal changes after anti-fuse programming

6 is a timing diagram showing a signal change after an anti-fuse repair

Explanation of symbols for the main parts of drawings

21: comparison unit 22: word line control unit

23: anti part 31: comparison unit

32: word line control unit 33: anti part

41: PMOS transistor 42: First NMOS transistor

43: anti-fuse unit 44: first inverter

45: second inverter 46: second NMOS transistor

47: third inverter 48, 49: first transfer gate

50: fourth inverter 51, 52: second transfer gate

Powerup: Power-Up Signal EN: Enable Signal

BXAR: Address Signal HIT: Hit Signal

VNEG: Negative Voltage Signal

The repair circuit of the semiconductor memory device of the present invention for achieving the above object is a comparison unit for receiving an address signal to the fuse set provided by the number of word lines to compare the hit of each fuse set to output a heat comparison signal And a word line controller for disabling the normal word line having a fail by receiving the heat comparison signal and disabling the normal word line, and enabling the redundant word line to replace the normal word line, and a redundant failure occurring after packaging. It is configured to include an anti-section to enable anti-redundant word lines by checking the hit for each address by driving an anti-fuse set program by receiving an address signal in place of a word line or a normal word line. It is done.

Hereinafter, a repair circuit of a semiconductor memory device of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a block diagram showing a repair circuit of a semiconductor memory device as a first embodiment of the present invention.

In the first embodiment of the present invention, the repair is performed before and after packaging the repair for the word lines of <0: 7>.

As shown in FIG. 2, the address signal BXAR <2:11> is applied to the fuse set <0: 7> provided by the number of word lines (the eight normal word lines in the first embodiment). The comparison unit 21 for comparing the hit of the fuse set and outputting the heat comparison signal HITB <0: 7> and the heat comparison signal HITB <0: 7>, and performing a heat sum processing. A word line controller 22 for disabling the failing normal word line NWL, replacing the normal word line, and enabling the redundant word line RWL, and the failing redundant word line RWL after packaging. Alternatively, an anti-fuse set program is driven by receiving an address signal BXAR <2:11> by substituting the normal word line NWL to check whether each address is hit, and performing a heat sum processing to perform an anti-redundant word line A_RWL. ) Is configured with an anti-23 to enable.

This will be described in detail as follows.

First, the comparator 21 responds to the fuse set enable signal FSE <>, and the hit signal HIT <0: 9> indicating whether or not a hit is performed on each of the signals BXAR <2:11>. ) And a heat comparison signal HITB <> of each fuse set by comparing the fuse set 201 having fuse units 201 and the heat signals HIT <0: 9> for each fuse unit in the fuse set 201. ), An arithmetic unit 202 is provided as many NWL <0: 7> as the number of normal wordlines.

At this time, the operation unit 202 is characterized in that it detects when all the heat signal (HIT <0: 9>) for each fuse unit is a high signal. To this end, the operation unit 202 is configured as a NAND gate element.

Secondly, the word line controller 22 receives the hit comparison signal HITB <> and outputs a normal word line disable signal NWD for disabling the normal word line, and drives a redundant word line unit. Redundant word line RWL <> to replace the normal word line in which a fail has been generated by receiving the hit island portion 203 for outputting an island signal HITSUM <> and the heat island signal HITSUM <>. And a redundant word line unit 204 for outputting a redundant enable signal RWL <>.

The anti-fuse 23 receives an address signal BXAR <2:11> and outputs a hit signal HIT <0: 9> for each address signal BXAR <2:11>. An anti-fuse set 205 including a unit, an anti-computing unit 206 for receiving the anti-fuse unit heat signals HIT <0: 9>, and comparing them to output an anti-heat comparison signal A_HITB; An anti-heat island portion (not shown in the drawing and using a heat island portion in the word line control unit) that receives an anti-heat comparison signal A_HITB and performs a heat island processing to output an anti-heat island signal A_HITSUM, and the anti-heat And an anti-word line driver 207 for receiving the island signal A_HITSUM to drive the anti-redundant word line A_RWL.

At this time, the anti-heat island portion of the anti portion 23 is not configured separately, and the heat island portion 203 of the word line controller 22 may be used.

In general, in a repair circuit composed of a normal word line and a redundant word line, repair is possible in a wafer process step, that is, before packaging, and occurs after packaging. The fail cannot be repaired with a conventional repair circuit configuration.

Therefore, the anti part 23 is configured to repair a package after packaging. The anti part 23 has a structure in which the comparator 21 and the word line control unit 22 are formed together.

3 is a block diagram showing a repair circuit of a semiconductor memory device according to a second embodiment of the present invention.

3, in the repair circuit of the second embodiment of the present invention, the structure of the comparator 21 and the word line controller 22 of the first embodiment is configured in the same manner, and the anti-control part 33 is changed as follows. do.

That is, the anti part 33 of the second embodiment receives the address signal BXAR <2:11> and receives the hit signal HIT <0: 9> for each address signal BXAR <2:11>. The anti-fuse set 305 including an anti-fuse unit for outputting the anti-fuse unit and the anti-fuse unit's hit signal HIT <0: 9> are applied to compare the anti-fuse comparison signal A_HITB <0: 7>. An anti-operation unit 306 for outputting the anti-heat comparison signal A_HITB <0: 7>, and a selection unit 307 for selecting and enabling a redundant word line RWL <> that is not used during repair before packaging. It is configured to include).

In this case, the selector 307 is a block for applying a selection signal to use the redundant word line RWL <> which is not used in the pre-packaging repair process, and is used to increase the integration degree of the semiconductor memory device. That is, by using the selection unit 307, the heat island portion of the anti portion and the anti-redundant word line may not be separately configured.

The repair method of the repair circuit of the semiconductor memory device of the present invention will be described with reference to FIG.

First, the repair of the pre-packaging step is performed using the comparator 21 and the word line controller 22.

Each fuse set receives an address signal BXAR <2:11> in response to the fuse set enable signal FSE and outputs a heat signal for each fuse unit.

If an address signal having a fail input is inputted, when the fuse set corresponding to the address is programmed, that is, the address signal is applied at a low level, the hit signals are all at a high level.

In this case, the fuse set enable signal FSE is a signal for selecting one of the redundant word lines RWL <> to be enabled, and the fuse set enable signal FSE is also cut by another fuse. ) Can be controlled according to the state.

If the fuse set enable signal <0> is enabled and the HIT <0: 9> signal is a high signal, HITB <0> is enabled.

This signal then enters the input of the wordline controller 22 and generates a signal that is a normal wordline disable (NWD) for disabling the normal wordline. At the same time, a heat island signal HITSUM <> is output through the heat island unit 203 to enable a redundant word line RWL <> to which each heat island signal is applied.

Up to this point, the process for repairing a fail bit of a normal word line is the same.

Then, when a failure occurs while packaging, repairing is impossible in the packaging state. In the present invention, the anti-part 23 is added to solve this problem.

That is, assuming that word line failure occurs after packaging, the anti-fuse set is activated by driving the anti-fuse set programming as follows.

The anti-fuse set has an anti-fuse set programming circuit built in the anti-fuse set to have a function of switching from an OFF state to an ON state when the word-line fail occurs after packaging.

4 is a circuit diagram illustrating the anti-fuse set programming unit of FIG. 2 or 3.

The anti-fuse set programming unit is a circuit provided in each of the anti-fuse units to which the address signal BXAR <2:11> is applied.

As shown in FIG. 4, a first terminal connected to the negative power supply voltage VNEG and an anti-fuse unit 43 connected to the other terminal of the anti-fuse 43 is controlled by the enable signal EN. The NMOS transistor 42, a first PMOS transistor 41 controlled by a power-up signal Powerup, and connected between a power supply voltage terminal and the first NMOS transistor 42, and the first NMOS transistor. A first inverter 44 for inverting the output of the common drain of the 42 and the first PMOS transistor 41, a second inverter 45 for inverting the output of the first inverter 44, and the first A second NMOS transistor 46 controlled by an output of the second inverter 45 and connected between an output terminal of the first inverter 44 and a ground voltage terminal, and an inverting output of the second inverter 45; Third inverter 47 and fourth for inverting address signal BXAR <> applied from outside The address signal BXAR <> is turned on when the butter 50 and the output of the second inverter 45 are applied to the NMOS 49 and the output of the third inverter 47 to the PMOS 48. To the PMOS 51 and the output of the third inverter 47 to the PMOS 51 and the first transmission gates 48 and 49 for outputting the signal as a heat signal HIT <>. And second transmission gates 51 and 52 that are applied to 52 to output the output of the fourth inverter 50 as a heat signal HIT <> when turned on.

In this case, the negative power supply voltage VNEG is applied from an output terminal thereof using a negative charge pumping circuit, and the negative charge pumping circuit may be configured inside or outside the semiconductor memory device.

5 is a timing diagram illustrating a signal change after anti-fuse programming.

As illustrated in FIG. 5, the anti-fuse set programming unit includes a clock signal CLK, a chip select signal CSB, a power-up signal Powerup, and an enable signal EN applied to the first NMOS transistor 41. Operate in response to

That is, before the anti-ON operation, the anti-fuse unit heat signal HIT <> transfers the address BXAR <> as it is by the power-up signal Powerup, and then after the anti-fuse set program ON. (Operation by applying the enable signal EN) The hit signal HIT <> has an inverted level of the signal BXAR <> of the address.

That is, when the address BXAR <> is a low signal, when the anti-fuse is turned on, all of the hit signals HIT <>, which are output signals of the program, are high signals.

For example, when a fail address of 00100001000 is input, when a portion corresponding to a low level address is programmed, all of the hit signals HIT <0> to HIT <9> are high level signals.

After the anti-fuse programming, the anti-hit comparison signal A_HITB is enabled to enable the anti-redundant word line A_RWL, and to disable the fail-normal word line or the previous repaired word line.

The role of the anti part is to accept a word line property or a bit line fail fail address after packaging, to disable the corresponding word line, and to enable the anti-redundant word line.

6 is a timing diagram illustrating a signal change after an anti-fuse repair.

As shown in FIG. 6, the anti-fuse unit-specific hit signals HIT <0: 9> are calculated through the anti-NAND unit to output an anti-heat comparison signal. That is, the anti-hit comparison signal is output as a low signal only when all of the hit signals are high signals, and the high signal is output in the other cases.

The anti-hit comparison signal is applied to a heat island portion of a word line driver in a semiconductor memory device to output an anti-heat island signal for enabling anti-redundant word line.

The anti hit island signal is output as a delayed signal by inverting the anti hit comparison signal.

When the anti-heat island signal is a high signal, relatively normal word lines and failed redundant word lines are disabled, and anti-redundant word lines are driven.

At this time, in the second embodiment, instead of the anti-redundant word line, a redundant word line which is not used during the repair before packaging is used.

The repair circuit of the semiconductor memory device of the present invention as described above has the following effects.

First, it is possible to repair not only a single bit failure that occurs after the packaging of the semiconductor memory device but also wordline failure.

Second, even when a repaired bit line is refailed, it can be repaired.

Third, in order to perform the repair by applying an anti-operating unit that operates in line instead of the anti-fuse which repairs one by one for the conventional single bit fail, the yield improvement effect of the semiconductor memory device can be obtained.

Claims (12)

A comparator configured to receive an address signal to a fuse set having a number of word lines and to compare a hit of each fuse set to output a hit comparison signal; A heat island unit configured to output a normal word line disable signal for disabling the normal word line by receiving the heat comparison signal, and output a heat island signal for driving a redundant word line unit, and fail to receive the heat island signal; A word line control unit including a redundant word line unit configured to output a redundant enable signal to enable a redundant word line to replace the generated normal word line; By replacing the redundant word line and normal word line that have failed after packaging, an anti-fuse set program is executed to switch from off to on when word line fail occurs after packaging. A repair circuit for a semiconductor memory device, comprising: an anti section for enabling an anti-redundant word line to be used as a repair word line that is enabled when the anti-fuse is repaired by performing a heat-sum treatment and a heat-sum treatment. The method of claim 1, wherein the comparison unit A fuse set comprising a fuse unit configured to output a hit signal indicating whether a hit is made to each signal of the address in response to a fuse set enable signal; And a calculation unit for comparing the heat signal of each fuse unit in the fuse set and outputting the heat comparison signal of each fuse set, the number of normal word lines. 3. The repair circuit of claim 2, wherein the operation unit detects when all of the heat signals for each fuse unit are high signals. The repair circuit of claim 3, wherein the operation unit comprises a NAND gate element. delete The method of claim 1, wherein the anti part An anti-fuse set comprising an anti-fuse unit receiving an address signal and outputting a hit signal for each address signal; An anti-computing unit for receiving the anti-fuse unit heat signal and comparing the anti-fuse unit to output an anti-heat comparison signal; An anti-hit island portion receiving the anti-hit comparison signal and performing a heat island processing to output an anti-heat island signal; And an anti-word line driver for receiving an anti-heat island signal to drive an anti-redundant word line. 7. The repair circuit of claim 6, wherein the anti-heat island portion of the anti portion is not configured separately, and the heat island portion of the word line controller is used. The method of claim 1, wherein the anti part An anti-fuse set comprising an anti-fuse unit receiving the address signal and outputting a hit signal for each address signal; An anti-computing unit for receiving the anti-fuse unit heat signal and comparing the anti-fuse unit to output an anti-heat comparison signal; And a selector configured to apply the anti-hit comparison signal to select and enable a redundant word line which is not used during repair before packaging. delete The method of claim 1, wherein the anti-fuse set program An anti-fuse unit with one terminal connected to the negative supply voltage, A first NMOS transistor controlled by an enable signal and connected to the other terminal of the anti-fuse unit; A first PMOS transistor controlled by a power-up signal and connected between a power supply voltage terminal and the first NMOS transistor; A first inverter for inverting the output of the common drain of the first NMOS transistor and the first PMOS transistor; A second inverter for inverting the output of the first inverter, A second NMOS transistor controlled by an output of the second inverter and connected between an output terminal of the first inverter and a ground voltage terminal; A third inverter for inverting the output of the second inverter, A fourth inverter for inverting an address signal applied from the outside, A first transfer gate receiving the output of the second inverter to NMOS and the output of the third inverter to PMOS and outputting the address signal as a heat signal when turned on; And a second transfer gate configured to apply the output of the second inverter to PMOS and the output of the third inverter to NMOS to output the output of the fourth inverter as a heat signal when turned on. Repair circuit of the device. 11. The repair circuit of claim 10, wherein the negative power supply voltage is applied from an output terminal thereof using a negative charge pumping circuit. 12. The repair circuit of claim 11, wherein the negative charge pumping circuit is configured outside the semiconductor memory device.