KR20000026318A - Repairing device - Google Patents

Abstract

PURPOSE: A repairing device is provided to diminish the size of chips and to perform a stable repairing operation with a high speed in a package level, by using an anti-fuse programming form without using a laser apparatus. CONSTITUTION: A repairing device comprises an address level controller(100), an anti-fuse programming unit(200), and a comparator(300). The address level controller decides column and row address levels according to a first control signal, enabled when a memory cell array fails. The anti-fuse programming unit controls whether or not the anti-fuse programming is generated, by selectively receiving first voltage applied when the first control signal is enabled and second voltage applied when a second control signal is enabled in a stand-by mode, by address signals outputted from the address level controller. The comparator receives the address signals, outputted in different electric potential according as whether or not the anti-fuse programming is generated, compares levels of the electric potential, and decides whether or not replacing to redundancy cells.

Description

Repair device

The present invention relates to a repair apparatus used to replace a defective cell in a semiconductor device with a redundancy cell. More specifically, the anti-fuse programming method enables repair at a package level as well as on a wafer. A repair apparatus for performing a repair operation.

1 is a circuit diagram illustrating a conventional repair apparatus, wherein a P-channel MOS transistor MP1 is applied with a precharge operation control signal pcg to a gate terminal and is connected between a power supply voltage Vcc applying terminal and a node N1; A plurality of laser cut fuses F1 to Fn connected in parallel to the node N1; A plurality of N-channel MOS transistors MN1 to MNn each of which is cut off in parallel between the laser cut fuses F1 to Fn and ground, and to which address signals axij_1 to axij_n are applied to respective gate terminals; An inverter (I1) connected to a rear end of the node (N1) to which the last fuse (Fn) is connected to invert a potential of the node (N1); The output terminal signal nrdb of the inverter I1 is fed back to the gate terminal and provided with a P-channel MOS transistor MP2 connected between the power supply voltage Vcc and the node N1.

In the conventional repair apparatus having the above configuration, when the precharge is performed, the precharge operation control signal pcg is applied low to charge the potential of the node N1 to the power supply voltage Vcc, and then the address for operating the chip. The precharge operation control signal pcg transitions high before the corresponding address of the signals axij_1 to axij_n is input.

Here, the address signals axij_1 to axij_n maintain a low level during operation standby, and only the address selected during operation is enabled high.

The N-channel MOS transistor, to which the high-enabled address signal is applied to the gate terminal, is turned on and discharged to the ground terminal through the fuse. Thus, the potential of the node N1 becomes low level, and a signal nrdb transitioned high through the inverter I1 is output, thereby controlling the normal cell to operate.

However, when a bad bit occurs in the chip and a corresponding defective cell is to be replaced by a redundancy cell, the fuse related to the corresponding address is blown using a laser beam with a strong output. . Thus, when the corresponding address is enabled, the corresponding transistors among the N-channel MOS transistors MN1 to MNn are turned on, but the fuse is blown, so the node N1 discharges the high potential to ground. It will not be able to do so and will remain at a high potential.

The potential of the node N1 that maintains the high potential outputs a low potential signal as a final output signal nrdb via an inverter I1 connected to a rear end thereof. In operation, the redundancy cell is replaced with the generating cell.

By the way, as described above, the conventional repair apparatus for determining whether to replace the redundancy cells due to the blowing of the laser-cut fuses, the material of the fuse (F1 ~ Fn) is made of a metal or polysilicon having a specific resistance component In addition, since the material covering the fuses F1 to Fn is a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ), there is a problem in that a high-speed repair operation is difficult.

In addition, in consideration of the laser interference of the laser equipment used for the blowing blow (fuse), the predetermined distance between the fuses is required, and because the width and length of each fuse should have a certain size or more, high integration technology situation Even under the design rule of the fuse, a predetermined limit is determined, which causes a problem that greatly affects the chip size.

In particular, in order to increase the repair yield, there is a problem that a large area is occupied in a row and column repair system in which a plurality of repair fuse boxes must be secured.

In addition, since the fuse blows with the laser equipment, only wafer-level repair is possible, and since the laser equipment is also an expensive product, there is a disadvantage in terms of cost.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to implement a simple circuit using an anti-fuse programming method instead of the laser cut fuse to reduce the size of the chip, and to provide stable and high speed at the package level. The present invention provides a repair apparatus that performs a repair operation.

1 is a circuit diagram showing a conventional repair apparatus

2 is a block diagram showing a repair apparatus according to the present invention.

3 is a detailed circuit diagram showing a first embodiment of the address level control means shown in FIG.

4 is a detailed circuit diagram showing a second embodiment of the address level control means shown in FIG.

5 is a detailed circuit diagram of the anti-fuse programming means shown in FIG.

6 is a detailed circuit diagram of the comparison means shown in FIG.

<Description of the symbols for the main parts of the drawings>

100: address level control means 200: anti-fuse programming means

300: comparison means

In order to achieve the above object, a repair apparatus according to the present invention comprises: address level control means for determining the level of a column and a row address according to a first control signal which is enabled when a memory cell array is defective;

The first voltage applied when the first control signal is enabled and the second voltage applied by the second control signal enabled in the standby mode of the normal operation are selected by the address signal output from the address level control means. Anti-fuse programming means for controlling whether or not to program the anti-fuse program;

And comparing means for receiving the address signals output at different potentials according to whether the anti-fuse is programmed, and comparing the potential levels to determine whether to replace the redundant cells.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a repair apparatus according to the present invention, wherein address level control means for determining the level of a column and a row address according to a control signal PB which becomes an enable state when a failure of a memory cell array occurs ( 100); The first voltage PVcc applied when the control signal PB is enabled, and the second voltage Vcc applied by another control signal PA enabled in the standby mode of the normal operation may be configured to the address level. Anti-fuse programming means (200) for controlling whether to program an anti-fuse by selectively transferring the address signals (axij_1 to axij_n) output from the control means (100); Comparison means 300 for receiving the address signals faxij_1 to faxij_n outputted at different potentials according to whether the anti-fuse is programmed, and comparing the potential levels to output a signal nrdb for determining whether to replace the redundant cells. ).

3 to 6 show detailed circuit diagrams of the address level control means 100, the anti-fuse programming means 200, and the comparison means 300 shown in FIG. 2, with reference to these figures. The detailed configuration and operation will be described.

First, FIG. 3 is a detailed circuit diagram showing a first embodiment of the address level control means 100 shown in FIG. 2, and receives column and row address signals Gaxij_1 to Gaxij-n, respectively, for selective switching operation. First and second switching units S1 and S2 for transmitting the address signals Gaxij_1 to Gaxij-n to nodes N1 and N2, respectively; First and second controllers 110 and 120 connected to output terminals N1 and N2 of the first and second switching units S1 and S2 to control levels of the address signals Gaxij_1 to Gaxij-n, respectively. )Wow; Third and fourth switching units S3 and S4 connected to the first and second control units 110 and 120 to transfer the level controlled address signal to the anti-fuse programming means 200 by a selective switching operation. It consists of

In the same figure, the first to fourth switching units S1 to S4 include a transfer gate, and the first and third switching units S1 and S3 have the control signal PB. When it is applied in the enable state (in the case of the figure, the low level) is turned on and the switching operation, the second and fourth switching unit (S2, S4) is the control signal (PB) is disabled (high level) When it is applied to), it is turned on and switching operation.

The first controller 110 may include an inverter I1 which inverts and transfers the potential of the output terminal N1 of the first switching unit S1; Each source terminal is connected to an output terminal N1 of the first switching unit S1 and an output terminal of the inverter I1, and each gate terminal is connected to an NMOS transistor MN1, which is connected to a power supply voltage Vcc applying terminal. MN2); A high voltage (PVcc) higher than the power supply voltage Vcc by a predetermined potential, and connected between an application terminal and a drain terminal of the NMOS transistors MN1 and MN2, respectively. PMOS transistors MP1 and MP2 having nodes N4 and N3 connected to drain terminals of the NMOS transistors MN2 and MN1 connected in cross-couple structures to their respective gate ends; The inverter I2 is connected to the node N4 and is connected between the high voltage PVcc applying terminal and the ground terminal.

In addition, the second control unit 120 includes an even number of inverters I3 and I4 connected in series (similarly, two in the case of the same figure).

In the address level control means 100 having the above configuration, the first and third switching units S1 and S3 are turned off by the control signal PB which is normally applied at a high level. Since the four switching units S2 and S4 are turned on, an address output from the turned-on second switching unit S2 via the second control unit 120 through the path to the fourth switching unit S4 is output. The level of the signals axij_1 to axij_n is controlled from the high level Vcc to the low level Vss.

On the contrary, when a failure occurs in the memory cell and the anti-fuse needs to be programmed, the first and third switching units S1, S3) is turned on, and the second and fourth switching units S2 and S4 are turned off. Accordingly, the level of the address signals axij_1 to axij_n output from the turned-on first switching unit S1 via the first control unit 110 and the third switching unit S3 is changed to the high level PVcc. ) To control the low level (Vss).

By the above operation, the level of the address signal transmitted during the normal operation and the fuse program operation is controlled differently.

In the figure, the first input column and row address signals Gaxij_1 to Gaxij_n are applied at the high (Vcc) level during operation standby, and the corresponding addresses are applied at the low (Vss) level during operation. .

FIG. 4 is a detailed circuit diagram showing a second embodiment of the address level control means shown in FIG. 2, and operates the first input column and row address signals Gaxij_1 to Gaxij_n as opposed to the address level control means shown in FIG. The circuit diagram shows the case where all are applied at the low (Vss) level during standby and the corresponding address is applied at the high (Vcc) level during operation.

Therefore, the inverter I5 is additionally configured in front of the first and second switching units S1 and S2 to which the address signals Gaxij_1 to Gaxij_n are applied, and the basic configuration and operation are the address shown in FIG. Since it is the same as the level control means, a detailed description thereof will be omitted.

FIG. 5 is a detailed circuit diagram of the anti-fuse programming means illustrated in FIG. 2, wherein the first power supply unit supplies a high voltage PVcc having a predetermined potential higher than the power supply voltage Vcc to the precharge node N2 ( 210; A second power supply unit 220 for transmitting a power supply voltage Vcc to the precharge node N2; The turn-on operation is connected between the second power supply 220 and the precharge node N2 and is controlled in accordance with a control signal PB applied in an enable state when a failure occurs, so that the high voltage PVcc and the power supply are controlled. A short circuit prevention unit 230 for preventing a short circuit from the voltage Vcc; A first switching unit 240 for transferring the potential of the precharge node N2 according to the potential level of the address signals axij_1 to axij_n output through the address level control means 100; Anti-fuses AF1 to AFn connected to the first switching unit 240; A second switching unit 250 connected between the anti-fuse AF1 to AFn and ground, and selectively switched to the ground terminal according to a control signal PC applied high when the chip is operated or when the fuse is programmed. do.

The control signal PB is applied to the gate terminal of the first power supply unit 210, and the second power supply unit 220 maintains a low level in the standby mode and then transitions to a high level when the operation mode is entered. PA is applied to the gate terminal, and the short circuit protection unit 230 includes each of the PMOS transistors MP1, MP2, and MP3 to which the inversion signal / PB of the control signal PB is applied to the gate terminal. do.

The first switching unit 240 includes a plurality of PMOS transistors MP4 to MPn + 3 connected in parallel to each other, and the second switching unit 250 includes a plurality of NMOS transistors MN1 to MNn connected in parallel to each other. It consists of.

Hereinafter, the operation of the anti-fuse programming means 200 having the above configuration will be described.

First, since the control signal PA is applied at a low level in the normal operation, the PMOS transistor MP2 is turned on. Thus, after precharging the precharge node N2 to the power supply voltage Vcc level, when the corresponding address signal for operation is applied, the control signal PA transitions to high. At this time, since the other control signal PB is at a high level, the PMOS transistor MP1 constituting the first power supply 210 is turned off and the PMOS transistor constituting the short circuit protection unit 230 ( MP3 is turned on because the inverted signal of the control signal PB is applied to the gate terminal.

Thereafter, among the address signals axij_1 to axij_n, a corresponding address signal for normal operation is enabled at a low level through the address level control means 100, and an unaddressed address signal continues to maintain a high level. As a result, only the PMOS transistor to which the corresponding address is applied to the gate terminal in the first switching unit 240 is turned on.

Then, the anti-fuse not programmed yet outputs the corresponding address signals faxij_1 to faxij_n at a high level through the turned-on PMOS transistor. At this time, the plurality of NMOS transistors MN1 to MNn constituting the second switching unit 250 are all turned on by the control signal PC applied high during chip operation or fuse programming. As described above, since the anti-fuse AF1 to AFn are not programmed as described above, the high level of the address signals axij_1 to axij_n does not flow to the ground terminal and is output as the output address signals faxij_1 to faxij_n. It is done.

However, when a defect occurs in the memory cell array and needs to be replaced with a redundancy cell, first, the corresponding address signal in which the defect occurs is inputted to the address level control means 100 and the control signal PB is applied at a low level. . Thus, the address signal is input at the low level of the ground potential, and an address signal that is not applicable is applied as the high level signal of the power potential, and the level of the address signal output through the address level control means 100 is the corresponding address. The low level of the ground potential is similarly output as the signal, but the high voltage PVcc higher than the power potential is output as the address signal that is not applicable. Here, the potential level of the high voltage PVcc should be a voltage sufficient to program the anti-fuse AF1 to AFn.

The PMOS transistor MP1 is turned on by the control signal PB applied at a low level, and a high voltage PVcc is supplied to the precharge node N2. At this time, since the PMOS transistor MP3 of the short circuit protection unit 230 is turned off, a short circuit between the power supply voltage Vcc and the high voltage PVcc can be prevented.

In addition, since all of the NMOS transistors MN1 to MNn constituting the second switching unit 250 are turned on by the control signal PC applied at a high level during programming, the high voltage PVcc is applied. A potential difference by the high voltage PVcc is generated from the node N2 that is precharged so that the anti-fuse is programmed.

As a result, the PMOS transistors to which the address signals which are not applied among the PMOS transistors MP4 to MPn + 3 in the first switching unit 240 are applied at the high voltage PVcc level are completely turned off to output address signals faxij_1 to A low level signal is outputted to faxij_n), and the turned-on PMOS transistor delivers the high voltage PVcc fetched to the precharge node N2 for the corresponding address signal applied at the low level of the ground potential Vss. However, the corresponding anti-fuse programmed to discharge the high voltage PVcc to the ground terminal. Therefore, a low level signal is similarly outputted as the output address signals faxij_1 to faxij_n.

That is, in the present invention, when a defect occurs in the memory cell array and needs to be replaced by a redundant cell, the anti-fuse programming means 200 outputs all of the output address signals faxij_1 to faxij_n at a low level.

FIG. 6 shows a detailed circuit diagram of the comparison means shown in FIG. 2, comprising: a precharge unit 310 for supplying a power supply voltage Vcc to the precharge node N3 according to the precharge signal pcg; A switching unit 320 connected between the precharge node N3 and a ground terminal and switched to the ground terminal by address signals faxij_1 to faxij_n outputted from the anti-fuse programming means 200; And an output driver 330 which buffers an output signal of the switching unit 320 and outputs a signal nrdb that determines whether to replace the redundant cell.

The precharge unit 310 includes a PMOS transistor MP1 to which the precharge signal pcg is applied to a gate terminal.

In addition, the switching unit 320 is provided with the address signals faxij_1 to faxij_n output from the anti-fuse programming means 200 to respective gate terminals, and are connected to a plurality of NMOS transistors MN1 to MNn connected in parallel with each other. It is composed.

In addition, the output driver 330 is connected to the rear end of the precharge node N3, and outputs a signal nrdb that determines whether or not to replace the redundancy cell to the output terminal, and the inverter I1 The output signal of is fed back to the gate terminal and is applied, and is composed of a PMOS transistor MP2 connected between the power supply voltage Vcc and the precharge node N3.

The operation of the comparison means 300 having the above configuration is as follows.

First, the electric potential of the precharge node N3 precharged to the power supply voltage Vcc by the precharge signal pcg before operation is switched by the corresponding address signals faxij_1 to faxij_n applied with a high level. By selectively turning on the NMOS transistor in the unit 320, it is discharged to the ground potential.

Therefore, a high level output signal nrdb is generated through the inverter I1 constituting the output driver 330, thereby performing normal operation, that is, normal row and column operations.

However, when all of the potential levels of the address signals faxij_1 to faxij_n output from the anti-fuse programming means 200 are low because of a failure in the memory cell array, the switching unit 320 in the comparison means 300. NMOS transistors (MN1, MNn) constituting the () is turned off so that the potential of the precharge node (N3) is still maintained at a high level. The potential of the precharge node N3 having the high level outputs a low level signal as an output signal nrdb via the inverter I1 in the output driver 330. Thus, by replacing the defective cell with a redundancy cell, the operation of the redundancy cell is performed.

As described above, the repair apparatus according to the present invention has a very excellent effect of simplifying the circuit configuration and reducing the chip area by using an anti-fuse having a simple structure for repairing defective cells.

In addition, repair can be performed without using a separate laser device, repair can be performed not only on the wafer but also at the package level, and it is effective to perform a stable repair operation at a high speed.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and changes fall within the scope of the claims Should be seen.

Claims (14)

Address level control means for determining a level of a column and a row address according to a first control signal which becomes an enabled state when a memory cell array is defective; The first voltage applied when the first control signal is enabled and the second voltage applied by the second control signal enabled in the standby mode of the normal operation are selected by the address signal output from the address level control means. Anti-fuse programming means for controlling whether to program the anti-fuse program; And a comparison means for receiving the address signals output at different potentials according to whether the anti-fuse is programmed, and comparing the potential levels to determine whether to replace the redundant cells with redundancy cells. The method of claim 1, And the second voltage is a power supply voltage, and wherein the first voltage is higher than the second voltage. The method of claim 1, The address level control means, First and second switching units receiving the column and row address signals, respectively, and transferring the address signals by a selective switching operation; First and second controllers connected to output terminals of the first and second switching units, respectively, to control levels of the transmitted address signals; And third and fourth switching units connected to the first and second control units to transfer the level-controlled address signal by a selective switching operation. The method of claim 3, wherein The first to fourth switching unit is made of a transfer gate; The first and third switching units are turned on when the first control signal is applied to the enabled state, and the switching operation. The second and fourth switching units are turned on when the first control signal is applied to the disabled state. Repair device, characterized in that the switching operation. The method of claim 3, wherein The first control unit includes a first inverter for inverting and transferring the output terminal potential of the first switching unit; First and second NMOS transistors each having a source terminal connected to an output terminal of the first switching unit and an output terminal of the first inverter, each gate terminal being connected to a power supply voltage applying terminal; A high voltage applied terminal higher than the power supply voltage by a predetermined potential and connected to the drain terminals of the first and second NMOS transistors, respectively, and the drain terminals of the second and first NMOS transistors have a cross-coupled structure at their respective gate ends. Connected first and second PMOS transistors; And an inverter connected to the drain terminal of the second NMOS transistor. The method of claim 3, wherein The second control unit is a repair device, characterized in that composed of an even number of inverters connected in series. The method of claim 1, The anti-fuse programming means includes a first power supply for supplying the first voltage to the precharge node; A second power supply unit transferring the second voltage to the precharge node; A short circuit prevention unit connected between the second power supply unit and the precharge node and controlling a turn-on operation according to the first control signal to prevent a short circuit between the first voltage and the second voltage; A first switching unit transferring a potential of the precharge node according to a potential level of the address signal output through the address level control means; An anti-fuse connected to the first switching unit; And a second switching unit connected between the antifuse and the ground and selectively switched to the ground terminal according to a third control signal. The method of claim 7, wherein The first and second power supply units are composed of PMOS transistors in which the first control signal and the second control signal are applied to the respective gate ends, and the short circuit prevention unit applies the inverted signal of the first control signal to the gate ends. A repair apparatus, comprising a PMOS transistor. The method of claim 7, wherein And the first switching unit includes a plurality of PMOS transistors connected in parallel to each other. The method of claim 7, wherein And the second switching unit includes a plurality of NMOS transistors connected in parallel to each other. The method of claim 1, The comparing means includes a precharge unit for supplying a power supply voltage to the precharge node according to the precharge signal; A switching unit connected between the precharge unit node and a ground terminal and switched to the ground terminal by an address signal output from the anti-fuse programming means; And an output driver for buffering an output signal of the switching unit and outputting a signal for determining whether to replace the redundant cell. The method of claim 11, The precharge unit is a repair device, characterized in that the precharge signal is applied to the gate terminal, the source terminal is composed of a PMOS transistor connected to the power supply voltage applying terminal. The method of claim 11, The switching unit is a repair device, characterized in that the address signal output from the anti-fuse programming means is applied to each gate end, and composed of a plurality of NMOS transistors connected in parallel. The method of claim 11, The output driver is connected to the rear end of the precharge node and the inverter, The output signal of the inverter is fed back to the gate terminal is applied, the repair device, characterized in that consisting of a PMOS transistor connected between the power supply voltage applying stage and the precharge node.