KR100562979B1 - Method and appratus for programming a repair address - Google Patents

Abstract

The repair address program method according to the present invention includes: programming data corresponding to an address to be repaired using a first antifuse to designate an address to be repaired; Checking whether data corresponding to the address to be repaired is normally programmed; Programming the first input signal using the second antifuse if the program is normally programmed as a result of the checking of the step; And blocking the reprogramming of the first antifuse according to a program state of the second input signal and the second antifuse.

Repair, antifuse

Description

Repair address program method and apparatus {Method and appratus for programming a repair address}

1 is a conventional repair address program circuit diagram.

2 is a repair address program apparatus according to the present invention;

3 is a detailed circuit diagram of the repair confirmation block shown in FIG. 2;

Explanation of symbols on the main parts of the drawings

A1, A2 ... AN: 1st, 2nd ... Nth repair address program block

50: repair confirmation block 60: combination circuit

The present invention relates to a repair address program method and apparatus, and more particularly, to a repair address program method and apparatus for preventing a repair address from being reprogrammed by a user according to a program result of the repair address.

As semiconductor integrated circuits develop, more circuit elements are included in a given silicon region. Reducing or eliminating defects in these circuit elements requires more circuit elements. To maximize die utilization and achieve higher densities, circuit designers are struggling to reduce the size of individual circuit elements. This reduction in size makes these circuit elements increasingly affected by defects due to impurities during the manufacturing process. Such defects should be identifiable by testing procedures upon completion of integrated circuit fabrication, or by semiconductor chip level or package completion. It is economically undesirable to discard defective integrated circuits when a defect is identified, especially when a small number of circuit elements are actually defective.

Expecting zero defects in the fabrication of integrated circuits is impractical. Thus, redundant circuits are provided in the integrated circuit to reduce the number of integrated circuits discarded. If the first device is determined to be defective, then the redundant circuitry replaces the defective circuitry. The actual reduction in discarded devices is achieved using redundant circuitry without a substantial increase in the cost of integrated circuit devices.

One integrated circuit that uses redundant circuitry is, for example, integrated memory circuits such as DRAM, SRAM, VRAM, and EPROM. Typical integrated memory circuits include a plurality of memories arranged in an array of addressable rows and columns. The memory in rows and columns is the first circuit element of the integrated memory circuit. By providing redundant circuitry, the defective first column, row, or individual bit can be replaced.

Since the first circuit elements of the individual integrated memory circuits can be addressed separately, the fuse control programmable circuit for programming the redundant circuits according to the fuse blowing or the address of the defective first circuit element to replace the defective elements. Requires antifuse. This process is very effective for permanently replacing defective devices.

For example, in the case of DRAM, a particular memory cell is selected by providing the row and column address where the particular memory cell is located. The redundancy circuit must recognize a valid first memory circuit element and cause all signals to be changed to the redundant circuit element when an address for the defective first circuit element is provided by the user. Thus, multiple fuses or antifuses are associated with each redundant circuit element. A possible combination of blown or unblown fuses corresponding to each redundant circuit element represents a single address of all the first devices that the corresponding redundant element will replace.

The anti-fuse is a device that serves as a switch that connects two electrodes by using breakdown in the structure of the electrode / insulator / electrode. The dielectric breakdown voltage of this insulator is called the anti-fuse program voltage (PGM), and the two electrodes are short-circuited through the program.

A circuit for programming a repair address using such an antifuse device is shown in FIG. Figure 1 is a conventional circuit developed to compensate for the disadvantage that can be repaired by laser cutting a fuse made of poly or metal in the wafer state, but can not repair defects generated in the package state. 1 is a method of re-testing even in a packaged state to identify a bad cell address when a bad memory cell is generated, and to designate a program address to always deal with a redundancy cell when an input related to a defective address comes in later. If the address to be repaired is high and the input anti_repair is high, the PMOS transistor S1 is turned on by the low potential of the first node N1 to generate a current path from the PMOS transistor to the Vss_anti terminal. . The stress is applied to the antifuse 10 by this current path, and the antifuse 10 is destroyed. Therefore, the second node N2 becomes low level and the output anti_address becomes high level. On the contrary, when the address to be repaired is at the low level, the PMOS transistor s1 is turned off because the first node N1, which is the output of the NAND gate 1, has a high potential regardless of the input (anti_repair). . Therefore, the output (anti_address) goes low. The combination of these outputs allows you to program faulty addresses so that redundancy cells are selected if the faulty address is used by some other factor.

Such a conventional antifuse method does not cause a problem in the case of a repaired address, but has a disadvantage in that a repair program can be performed by mistaken by a normal address as a defective address by a user other than the producer. In addition, there is a drawback that you cannot check whether the anti-fuse program has been programmed normally to repair.

Accordingly, an object of the present invention is to provide a repair address program method and apparatus for checking whether the antifuse device is normally programmed after programming the antifuse.

It is another object of the present invention to provide a repair address program method and apparatus that prevents a user from reprogramming a repair completed address after the repair is completed by the producer.

In order to achieve the above object, a repair address program method includes: programming data corresponding to an address to be repaired using a first antifuse to designate an address to be repaired;

Checking whether data corresponding to the address to be repaired is normally programmed;

Programming the first input signal using the second antifuse if the program is normally programmed as a result of the checking of the step;

And blocking the reprogramming of the first antifuse according to a program state of the second input signal and the second antifuse.

A repair address program for achieving the above object means for programming data corresponding to an address to be repaired using a first antifuse to specify an address to be repaired;

A repair confirmation block for programming a first input signal using a second antifuse when the address to be repaired is normally programmed;

And a combination circuit for generating a signal for interrupting reprogramming of the first antifuse according to the output signal and the second input signal of the repair confirmation block.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a block diagram of a repair address program device having a repair confirmation and blocking function according to the present invention.

First to Nth repair address program blocks A1 to AN are provided. Each of the first to Nth repair address blocks A1 to AN has the configuration of FIG. 1. In addition, the repair address program apparatus having a repair confirmation and blocking function according to the present invention includes a repair confirmation block 50 and a combination circuit 60. The combination circuit 60 includes a Noah gate and an inverter connected in series, and repair. The detailed configuration of the confirmation block 50 is as shown in FIG. In addition, the output (anti_program) of the repair confirmation block 50 is connected to the input terminal (anti_program) of the combination circuit 60, the output (anti_repair) of the combination circuit is connected to each repair address program block (A1 to AN). .

The operation of FIG. 2 will be described in detail with reference to FIGS. 1 and 3.

In the initial state, an address applied to each of the repair address blocks A1 to AN is in a low state, and an address is not input to the address input terminal address B of the combination circuit 60. An output of anti_repair outputs a low signal. As a result of testing the memory device, when an attempt is made to program a defective address, a separate address (address B) other than the address to be repaired becomes high and the output (anti_repair) of the combination circuit 60 becomes high. do. This high signal is input to each repair address program block A1 to AN. In the address terminals of each repair address program block A1 to AN, an address of a binary system (for example, 000 ... 1) is input to indicate an address to be repaired. Therefore, only the address program block to which the high signal is input among the address input terminals of the repair address program blocks 1 to N is programmed. If the address is high as described in FIG. 1, the first node N1, which is the output of the NAND gate 1. Becomes low and accordingly, the PMOS transistor s1 is turned on and the anti-fuse 10 is insulated and destroyed, thereby creating a current path between the second node N2 and the Vss_anti terminal. ) Goes low, so the inverter's output (anti_address) goes high.

On the contrary, when the low signal is input to the address input terminal of the repair address program block, the first node N1, which is the output of the NAND gate 1, becomes high as described with reference to FIG. 1, and the PMOS transistor s1 Is turned off. Therefore, the second node N2 is turned on so that the output of the inverter anti_address becomes low. After programming the repair address in this way, you can check whether the repair address has been correctly programmed by exiting the program mode informing the address to be repaired and retesting.

When a test result indicating that the repair address is normally programmed, a high signal is input to the address input terminal (address A) of the repair confirmation block 50. As shown in FIG. 2, the PMOS transistor s2 is turned on because the tenth node N10 is turned low. Therefore, the anti-fuse 20 is broken down to form a current path between the twentieth node N20 and the Vss-anti terminal. The output terminal anti_program remains low.

Since the address input terminal address B of the combination circuit 60 is low and the output anti_program of the repair confirmation block 50 is low, the output of the combination circuit 60 is low. Therefore, even if an attempt to reprogram the address to be repaired does not turn on the PMOS transistor s1 of FIG. 1, the antifuse 10 cannot be programmed. Therefore, the address to be repaired by the user or the like can be prevented from being reprogrammed.

As described above, according to the present invention, not only the limited repair method using laser cutting in the existing wafer state is possible in the package state, but also when the match is made by specifying a defective address reliably at the time of repair, Since the program can be re-checked, the yield can be improved, and the reliability of the memory device can be further improved by blocking a path so that a repair is not performed when entering a reprogram that may be generated by a user.

Claims (6)

Programming data corresponding to the address to be repaired using the first antifuse to specify an address to be repaired; Checking whether data corresponding to the address to be repaired is normally programmed; Programming the first input signal using the second antifuse if the program is normally programmed as a result of the checking of the step; And blocking the reprogramming of the first antifuse according to the second input signal and the program state of the second antifuse. Means for programming data corresponding to the address to be repaired using the first antifuse to specify an address to repair; A repair confirmation block for programming a first input signal using a second antifuse when the address to be repaired is normally programmed; And a combination circuit for generating a signal for blocking the reprogramming of the first antifuse according to the output signal and the second input signal of the repair confirmation block. The method of claim 2, The combination circuit includes a NOR gate for combining the second input signal and an output signal of the repair confirmation block; And an inverting element for inverting the output of the NOR gate. The method of claim 2, The repair confirmation block may include a switching element for switching a power supply voltage according to the first input signal; An antifuse programmed by a power supply voltage supplied according to an operation of the switching element; And an output means for outputting a logic signal according to the program state of the antifuse. Means for programming data corresponding to the address to be repaired using the first antifuse to specify an address to repair; A switching element for programming a first input signal by using a second antifuse when the address to be repaired is normally programmed and switching a power supply voltage according to the first input signal, and a power supply supplied according to an operation of the switching element A repair confirmation block comprising an antifuse programmed by a voltage and an output means for outputting a logic signal according to a program state of the antifuse; And a combination circuit for generating a signal for blocking the reprogramming of the first antifuse according to the output signal and the second input signal of the repair confirmation block. The method of claim 5, The combination circuit includes a NOR gate for combining the second input signal and an output signal of the repair confirmation block; And an inverting element for inverting the output of the NOR gate.

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