GB2341714A

GB2341714A - Active matrix LCD driving method

Info

Publication number: GB2341714A
Application number: GB9922112A
Authority: GB
Inventors: Hyun Chang Lee
Original assignee: LG Philips LCD Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 1998-09-19
Filing date: 1999-09-17
Publication date: 2000-03-22
Anticipated expiration: 2019-09-17
Also published as: JP2007304613A; KR20000022668A; JP4259691B2; FR2783629B1; DE19944724A1; JP2000137247A; DE19944724B4; JP4764856B2; KR100700415B1; GB2341714B; FR2783629A1; GB9922112D0

Abstract

An active matrix liquid crystal display with a plurality of gate and data lines and a switching transistor at the intersection of these lines includes a gate driver with a shift register that receives at least two voltages and outputs at least one of these voltages to sequentially drive the pixels. One of the voltages changes before the application of the next voltage to reduce the flicker effect of driving switching transistors with waveforms with sharp transitions.

Description

2341714 ACTIVE MATRIX LIQUID CRYSTAL DISPLAY This invention relates to an

active matrix liquid crystal display, and more particularly, to an active matrix liquid crystal display, wherein it is provided with a device for applying a gate pulse to transistors connected to picture elements (or pixels) consisting of a liquid crystal.

The conventional active matrix liquid crystal display apparatus displays a picture by controlling the light transmissivity of liquid crystal using an electric field. As shown in Fig. 1, such a liquid crystal display apparatus includes a data driver 12 for driving signal lines SL I to SLm at a liquid crystal panel 10, and a gate driver 14 for driving gate lines GL I to GLn at a liquid crystal panel 10. In the liquid crystal panel 10, pixels I I connected to signal lines SL and gate lines GL are arranged in an active matrix pattern.

Each pixel I I includes a liquid crystal cell Clc for responding to a data voltage signal DVS from the signal line SL to control a transmitted light quantity, and a thin film transistor (TFT) CNN for responding to a scannina si2nal SCS from the gate line GL to switch the data voltage signal DVS to be applied from the signal line SL to the liquid crystal cell Clc. As the gate lines GL I to GLn are sequentially driven, the data driver 12 applies the data voltage signal DVS to all the signal lines SL I to SLm. The gate driver 14 allows the gate lines GLI to GLn to be sequentially enabled for each horizontal synchronous interval b applying the scanning signal SCS to the gate lines GL I to GLn y 0 0 sequentially. To this end, the gate driver 14 consists of a shift register 16 responding to a 0 gate start pulse GSP from a control line CL and a gate scanning clock GSC from agate clock line GCL, and a level shifter 18 connected between the shift register 16 and the 2 gate lines GL I to GLn. The shift register 16 outputs the gate start pulse GSP from the control line CL to any one of n output terminals QT I to QTn and, at the same time, responds to the gate scanning clock GSC to shift the gate start pulse GSP from the first output terminal QT I to the nth output terminal QTn sequentially. The level shifter Is cenerates n scanning signals SCS by shifling voltage levels of the ourput signals of the shift register 16. To this end, the level shifter 18 consists of n inverters 19 that are connected between the n output terminal QT I to QTn the shift register 16 and the n gate -:1 1= lines GL I to GLn, respectively, and fed with low and high level gate voltages Val and Vgh in a direct current shape from a first and a second voltage line FVL and SVL, respectively. The inverters 19 selectively supply any one of the low and high level gate 0 voltages Vg I and Vgh to the gate line GL in accordance with a logical state at the output terminal QT of the shift register 16. Accordingly, only one of the n scanning signals SCS -- 0 has the high level gate voltage Vah.

In this case, the TFT CMN receiving a scanning signal SCS having the high level gate voltage Vgh from the gate line GL is turned on, and the liquid crystal cell Clc charges the data voltage signal DVS during an interval when the TFT CMN is turned on. The voltage charged into the liquid crystal cell Clc in this manner drops down when the TFT CMN is tumed off and therefore becomes lower than a voltacre of the data voltage signal DVS. Accordingly, a feed through voltage Vp corresponding to a difference of voltage between the voltage charged in the liquid crystal cell and the data voltage signal DVS, is generated. This feed through voltage)Vp is caused by a parasitic capacitance existing between the gate terminal of the TFT CMN and the liquid crystal cell Clc, which changes a transmitted light quantity at the liquid crystal cell Clc periodically. As a result, a flicker and a residual image are generated at a picture displayed on the liquid crystal panel.

In order to suppress such a feed through voltage)Vp, as shown in Fig. 1, support capacitors Cst are connected, in parallel, to the liquid crystal cells. The support capacitor Cst compensates for the liquid crystal cell voltage when the TFT CNLN is turned off, thereby suppressing the feed through voltage)Vp as expressed in the following fbrmula 3 Vp= --(Von-Voff)lep_ CIC + Cst - Cas in which Von represents a voltage at the gate line GL upon turning on of the TFT CmN; Voff represents a voltage at the gate line GI, upon turning off of -.he TFT CMN; and C as represents a capacitance value of a parasitic capacitor existing between the Zgate terminal of the TFT CNIN and the liquid crystal ceil. As seen from formula (1), the feed through voltage)Vp increases depending on a voltage difference at the gate line GL upon turning- Z5 W on and turning off of the TFT C'i/C1.

In order to sufficiently suppress the feed through voltage)Vp. a capacitance value of the support capacitor Cst must be increased. This causes aperture ratio of display area to be decreased, so that it is impossible to obtain a sufficient display contrast. As a result, it is difficult to suppress the feed through voltage)Vp sufficiently by means of the 15 support capacitor Cst.

As another alternative for suppressing the feed through voltage)Vp, there has been suggested a liquid crystal display apparatus adopting a scanning signal control 0 W system for allowing the falling edge of the scanning signal SCS to have a gentle slope. In the liquid crystal display apparatus of a scanning signal control system, the falling edge of the scanning signal SCS changes in the shape of a linear function as shown in Fig. 2A, an exponential function as shown in Fig. 2B, or a ramp function as shown in Fig. 2C. Examples of such a liquid crystal display apparatus of scanning signal control system are disclosed in the Japanese Patent Laid-Open Gazette Nos. 1994-1100-3) 5 and 1997-258174 and the U.S. Patent No. 5,587,722. However, these liquid crystal display devices of a scanning signal control system additionally require a circuit modification of the gate driver or a new waveform modifying circuit to be positioned between the gate driver and each gate line at the liquid crystal panel. The gate driver described in the U. S. Patent No.

W 5,587,722 has a complex circuitry and consumes a great amount of power, because a circuit allowing the falling edge of the scanning signal to be stepwise is formed in a gate 310 driver chip.

For example, as shown in Fig. 3 3, the liquid crystal display apparatus of a scanning signal control system disclosed in the Japanese Patent Laid-Open Gazette No. 1994- 4 11003 5 includes an integrator 22 connected between a scanning driver cell 20 and a (rate line GL. The integrator 22 consists of a resistor R I between the scanning driver cell 20 and the gate line GL, and a capacitor C I connected between the gate line GL and the ground voltage line GVL. The integrator22 intearates a scanning signal SCS to be applied from the -ate driver cell 20 to the gate line GL, thereby changing the falling edcre of the scanning signal SCS into a shape of exponential function. tk TFT CINLN.- included in a pixel I I is turned on until a voltage of the scanning signal SCS from the -ate line GL drops less than its threshold voltage- At this time, an electric charcre charged in a liquid C.) =1 crystal cell Clc is pumped into the gate line GL through Cgs. However, sufficient electric _P charge is charged into the liquid crystal cell Clc by means of a data voltage signal DVS passing through the TFT CMN &om a signal line SL. A-s a result, the voltage charged in the liquid crystal cell Clc does not drop. Then, since a voltage variation amount in the gate line GL is a maximum threshold voltage of the TFT CMN when a voltage of the scanning signal SCS at the crate line GL drops less than a threshold voltage of the TFT CMN, electric charge amount pumped from the liquid crystal cell Clc into the crate line GL becomes very small. As a result, the feed through voltage)Vp can be suppressed sufficiently.

In the liquid crystal display apparatus of a scanning signal control system as described above, since the feed through voltage)Vp is suff iciently suppressed to reduce a 1 1.7 1 flicker and a residual image considerably but a waveform modifying circuit, such as an integrator, for each gate line must be added, the circuit configuration thereof becomes very complex. Further, because the rising edge of the scanning signal also changes slowly due to the waveform modifying circuit, a charge initiation time at the liquid crystal cell is delayed.

Meanwhile, the U.S. patent No. 5,587,722 discloses a shift register 3 selectively receiving power supply voltages VVDD and VVDD-Rl/(RI+R2), as shown in Fig. 4.

The shift register 3) responds to the supply voltages VVDD and VVDDRl/(RI --R2) and generates a stepwise pulse. However, the shift register 3 3 must be driven at a high voltage because the supply voltage VVDD is equal to a high-level gate voltage to be applied to gate lines on the liquid crystal display panel. In other words, inverters 5, 6 and 9 included in the shift register 3 operate at about 25 V of the driving voltage, if maximum voltage for turning on the TFT is a voltage of 2.5. Due to this, the active matrix liquid crystal display apparatus, disclosed in U.S. patent No. 5,587,722, consumes a large amount of power.

Accordingly, it is an object of the present invention to provide a liquid crystal display apparatus and method that is adapted to eliminate flickering and residual images g as well as to simplify the circuit configuration thereof Additional features and advantages of the invention will be set forth in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to achieve this and other objects of the invention, a liquid crystal display apparatus according to one embodiment of the present invention includes a plurality of pixels including switching transistors, each switching transistor havirg an electrode connected to a pixel electrode and a gate electrode- a plurality of data signal lines connected to the electrode associated with any one of the transistors; a plurality of gate signal lines connected to the gate electrode associated with any one of the transistors; and a gate driver connected to the plurality of gate signal lines. The gate driver receives first and second voltages and outputting at least one of the first and second voltages in such a manner to sequentially drive the gate signal lines, the first voltage changing prior to driving successive gate signal lines. The gate driver includes a shift register for - generating scanning signals to be applied respectively to the gate lines, wherein the shift register is responsive to a gate scanning clock; a level shifter making use of the first and second voltages to generate each voltage level of the scanning signals, and a voltage controller for changing the first voltage applied to the level shifter prior to disabling of the scanning signals. Preferably, a minimum value of the first voltage is higher than a 1) I-M maximum value of the second voltage.

According to one aspect of the present invention, the first voltage decreases prior to driving of the successive gate signal lines. In particular, the first voltage decreases exponentially, linearly or stepwisely- 6 According to another aspect of the present invention, the voltage controller includes a switch for cutting off the first voltage applied to the level shifter prior to disabling of the scanning signal; and a discharging path provided to the level shifter during period in which the scanning signal is cut off by means of the switch. The switch and the shift register respond to the gate scanning clock. The voltage controller may also include a timing controller for controlling the switch.

Alternatively, the voltage controller includes an input terminal for receiving the first voltage- a first resistor connected between the input terminal and an input port of the level shifter; a first control switch and a second resistor connected in series between the input port of the level shifter and a ground voltage line- and a second control switch connected in parallel to the first resistor, the second control switch being driven alternatively with the first control switch.

According to another aspect of the present invention, the voltage controller comprises a switch responsive to a gate output enable signal and is connected between the first voltage and the level shifter. Preferably, the gate output enable signal is inverse of the gate scanning clock.

A method of driving a liquid crystal display apparatus according to another aspect of the present invention includes the steps of inputting a first voltage and a periodically changing second voltagge; supplying the second voltage, via a switching device, to the Z7 C) g I I Z gate line; and supplying the first voltage, via the switching device, to the gate line, the n Z switching device being controlled by the shift register, wherein a minimum value of the second voltage is higher than a maximum value of the first voltage.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide 25 further explanation of the invention as claimed.

Specific embodiments will now be described, by way of example, with reference to the accompanying drawings, in which 7 Fig. 1 is a schematic view showing the configuration of a prior liquid crystal display device; Figs. 2A to 2C are waveform diagrams of a scanning signal having the falling edge changed slowly Fig. 3) shows a prior liquid crystal display apparatus employing the scanning si _gnal of Fig. 2B1 Fig. 4 is a schematic diagram showing the configUration of a prior liquid crystal Z display apparatus.

Fig. 5 is a schematic diagram showino, the configuration of a liquid crystal display apparatus according to a first embodiment of the present invention; Fig. 6 is a schematic diagram showing the configuration of a liquid crystal display apparatus according to a second embodiment of the present Invention; Fig. 7 is output waveform diagrams of each part of the liquid crystal display apparatus shown in Fig. 6) is Fig P. 8 is a schematic diagram showing the configuration of a liquid crystal display apparatus according to a third embodiment of the present invention; Fig. 9 is waveform diagrams of a high level gate voltage and a scannina signal; C = C> Fig. 10 is a schematic diagram showing the configuration of a liquid crystal display apparatus according to a fourth embodiment of the present invention; Fi =. 11 is a schematic diagram showing the configuration of a liquid crystal display apparatus according to a fifth embodiment of the present invention; Fig. 12 is waveform diagrams of a scanning signal and a data voltage signal each C) ZP =1 developed on gate line and signal line of the liquid crystal display apparatus according to the first to fifth embodiments of the present invention; Fig. 13) is a schematic diagram showing the configuration of a liquid crystal display apparatus according to a sixth embodiment of the present invention, Fig. 14 is output waveform diagrams of each part of the liquid crystal display apparatus shown in Fig. 13; Fig. 15 is waveform diagrams of a scanning signal and a data voltage signal each developed on gate line and signal line of the liquid crystal panel as shown in Fig. 13); 8 Fig. 16 is a schematic diagram showing another embodiment of the voltage controller shown in Fig. 13; Fig. 17 is a waveform diagram showing input and an output signal of the voltage controller as shown in Fig. 161 Fig. 18 is a schematic diagram showing the configuration of a liquid crystal display apparatus according to a seventh embodiment of the present invention., Fig. 19 is an output waveform diagram showing signals of each part of the liquid crystal display apparatus shown in Fig. 6; Fi& 20 is a schematic circuit diagram showing a line scanning circuit for driving 1:1 C) any one of the gate lines included in the liquid crystal display apparatus shown in Fig. 18 Fig. 21 is a schematic diagram showing the configuration of a liquid crystal display apparatus according to an eighth embodiment of the present inventionI 1 Fig. 22A is a waveform diaerram showing a scanning signal generated by the liquid crystal display apparatus according to the present invention; Fig. 22B is a waveform diagram showing a scanning signal generated by the prior liquid crystal display apparatus; Fia. 23)A is a waveform diagram showing a current characteristic developed on 0 the liquid crystal display apparatus according to the present invention; Fig. 2-33B is a waveform diagram showing a current characteristic developed on a prior liquid crystal display apparatus; Fig. 24 is a circuit diagram showing in detail the voltage controller shown in Fig. 21; Fig. 25 shows a tab type of liquid crystal display apparatus according to the present invention; and Fig. 26 shows a COG type of liquid crystal display apparatus according to the present invention.

Referring to Fig. 5, there is shown a liquid crystal display apparatus according to a first embodiment of the present invention that includes a data driver 32 for driving signal lines SL 1 to SLm on a liquid crystal panel 3 W, and a gate driver 34 for driving gate 9 lines GLl to GLn on the liquid crystal panel 30. In the liquid crystal panel 30, pixels 31 connected to si nal lines SL and gate lines GL are arranged in an active matrix pattern.

9 0 Each pixel 33 1 includes a liquid crystal cell Clc for responding to a data voltage signal DVS from the signal line SL to control a transmitted light quantity, and a thin film transistor (TFT) CMN for responding to a scanning signal SCS fforn the gate line GL to switch the data voltage signal DVS to be applied from the signal line SL to the liquid crystal cell Clc. Also, each pixel 31 has a support capacitor Cst connected, in parallel, to the liquid crystal cell Clc. This support capacitor Cst serves to buffer a voltage charged in the liquid crystal cell CIc. As the gate lines GL I to GLn are sequentially driven, the 10 data driver 33 2 applies the data voltage signal DVS to all the signal lines SL I to SLm. The aate driver 34 allows the gate lines GL I to GLn to be sequentially enabled for each horizontal synchronous interval by applying the scanning signal SCS to the gate lines GL I to GLn sequentially.

The -ate driver 34 has a shift register 36 respondino, to a aate start pulse GSP 0 0 -1) - from a control line CL and a (),ate scannino, clock GSC from a -ate clock line GCL, and M further has a level shifter 38 connected between the shift register 336 and the gate lines 7 GL I to GLn. The shift register 36 outputs the gate start pulse GSP from the control line CL to one of n output terminals QT I to QTn and, at the same time, responds to the gate 0 scanning clock GSC to shift the gate start pulse GSP from the first output terminal QT I to the nth output terminal QTn sequentially. Also, the shift register 36 operates at an integrated circuit driving voltage VCC having 5 V corresponding to a logical voltage level.

The level shifter '18 generates n scanning signals SCS by shifting voltage levels of the output signals of the shift register 336. To this end, the level shifter 3) 8 includes n control switches ') 9 connected between the n output terminal QT I to QTn of the shift register 36 and the n gate lines GL, respectively, to switch low and high level gate voltages Vgl and Vgh from first and second voltage lines FVL and SVL, respectively. The control switch 39 selectively delivers any one of the low and high level gate voltages Vg I and Vgh to the gate line GL in accordance with a logical state at the output terminal QT of the shift register 36. Accordingly, only one of the n scanning signals SCS has the high level gate voltage Vgh. In this case, the TFT CMN at the crate line GL supplied with 0 the high level c, ate voltage Vgh is turned on and thus the liquid crystal cell Clc charges the data voltage signal DVS during an interval when the TFT OVIN is turned on. Each control switch -339 may be replaced by a buffer in which the low and high level gate voltages Vgl and Vgh are its operation voltage.

The liquid crystal display apparatus according to the first embodiment of the present invention further includes a low level gate voltage generator 40 connected to the first voltage line FVL and a high level crate voltage crenerator 42. The low level gate 1 ID voltage generator 40 generates a low level crate voltage Val maintaining a constant voltage level or alternating periodically and supplies it to the n control switches 39 connected to the first voltage line FVL. The low level crate voltage Vgl generated at the low level voltage generator 40 may have a shape of an alternating current signal, such as a certain period of pulse signal.

The high level crate voltage generator 42 generates a high level crate voltage Vgh, Z 0 Z7 changing in a predetermined shape every period of horizontal synchronous signal, such as an alternating current signal. The high level gate voltage Vgh has a falling edge, Cl 1-11 changing slowly. The falling edge of the high level crate voltage Vgh is changed into the shape of a linear function, an exponential function, or a ramp function.

In order to generate such a high level gate voltage Vgh, the high level gate voltacre 1 -7 0 generator 42 includes a high level voltage generator 44 for generating a high level voltage, a voltage controller 46 connected between the high level voltage generator 44 and the second voltage line SVL, and a timing controller 48 for controlling a level control time of the voltage controller 46. The high level voltage generator 44 supplies a high level voltage VDD in the shape of direct current, maintaining a constant voltage level stably to the voltage controller 46. The voltage controller 46 periodically delivers the high level voltage VDD to the n control switches 39 connected to the second voltage line SVL and, at the same time, allows a voltage supplied to the second voltage line SVL to be lowered into any one of the function shapes mentioned above.

In order to change the falling edge of the voltage signal at the second voltage line SVL slowly, the voltage controller 46 may make use of a parasitic resistor Rp and a parasitic capacitor Cp existing in the gate lines GL of the liquid crystal panel 3)0. The timing controller 48 responds to a horizontal synchronous signal HS from a synchronization signal line SCL and a data clock DCLK &om a data clock line DCL to determine a voltage switching time and a voltage control time of the voltage controller 46. To this end, the timing controller 48 may include a counter that is initialized by the horizontal synchronous signal HS and counts the data clock DCLK, and a logical combiner (not shown) for logically combining output signals of the counter to control the voltage controller 46.

As described above, since the high level gate voltage Vgh at the second voltage -> 1:1 -M 1 line SVL has a failing edge changing into the alternating current shape and decreasing slowly, the failing edge of the scanning signal SCS applied to the gate line GL of [he liquid crystal panel -3) 0 changes slowly. The TFT ONN included in the pixel ') I is turned on until a voltage of the scanning signal SCS from the gate line GL drops less than its threshold voltage. At this time, electric charge stored in a liquid crystal cell Cie is pumped into the gate line GL, but sufficient electric charge is charged into the liquid 0 crystal cell Cie by means of a data voltage signal DVS passing through the TFT CMN from a signal line SL. Accordingly, the voltage charged in the liquid crystal cell Cie does not drop. Then, since a voltage variation amount in the gate line GL is a maximum M threshold voltage of the TFT CMN when a voltage of the scanning signal SCS at the gate line GL drops less than a threshold voltage of the TFT CNRi, electric charCre amount pumped from the liquid crystal cell Cie into the gate line GL becomes very small. As a result, a feed through voltage)Vp can be suppressed sufficiently- ReferTing now to Fig. 6, there is shown a liquid crystal display apparatus according to a second embodiment of the present invention. 'In the liquid crystal display apparatus of Fig. 6, a voltage controller 46 makes use of a parasitic resistor Rp and a parasitic capacitor Cp at a gate line GL to change the falling edge of a high level gate voltage Vgh and the falling edge of a scanning signal SCS into an exponential function shape. The liquid crystal display apparatus of Fig. 6 has a gate driver 3)4 for driving a gate line GL on a liquid crystal panel 30. The liquid crystal panel 30 Includes a pixel 31 connected to a signal line SL and the gate line GL. The pixel 3) I includes a liquid crystal cell Cie for responding to a data voltage signal DVS from the signal line SL to control a transmitted light quantity, and a TFT CMN for responding to a scanning signal SCS from the gate line GL to switch the data voltage signal DVS to be applied ftom the signal line 12 SL to the liquid crystal cell C1c. Also, the pixel 31 has a support capacitor Cst connected, in parallel, to the liquid crystal cell C1c.

In the second embodiment, the gate driver.334 consists of a shift register cell 56A responding to a gate start pulse GSP &om a control line CL and a gate scanning clock GSC from a gate clock line GCL, and a control switch '39 connected between the shift register cell 336A and the gate line GL. The shift register cell 336.A outputs the gate start pulse GSP at the rising edge of the gate scanning clock GSC as shown in Fig. 7 to an output terminal QT. The control switch 339 selectively delivers one of the low and high level gate voltages VgI and Vah to the gate line GI, in accordance with a logical state at Z> CP C.1 the output terminal QT of the shift register cell 36A.

Accordingly, a scanning signal SCS, having the low level gate voltage VgI or the high level gate voltage Vgh, emerges at the gate line GL. More specifically, the control switch 39 allows the high level gate voltage Vah to be supplied to the gate line GL when an output signal of the shift register cell 336A has a high logic; while it allows the low =1.P level gate voltage VgI to be supplied to the gate line GL when an output signal of the shift register cell 3)6A has a low logic. A signal "SCSn" in Fig. 7 represents a waveform of a scanning signal applied to the next gate line.

0 The liquid crystal display apparatus according to the second embodiment of the present invention further includes a low level gate voltage generator 40 connected to the 20 first voltage line FVL, and a high level gate voltage generator 42. The low level gate 0 0 C-5 voltage generator 40 generates a low level gate voltage VgI maintaining a constant 1 voltage level and supplies it to the control switch 9 connected to the first voltage line FVL. The high level gate voltage generator 42 generates a high level gate voltage Vgh, 0 Z5 0 W changing periodically as shown in Fig. 7. The falling edge of the high level gate voltage W W 0 Vgh drops slowly in an exponential function shape. In order to generate such a high level W gate voltage Vgh, the high level gate voltage generator 42 includes a high level voltage 0 c) 0 generator 44 for generating a high level voltage VDD and a voltage controller 46 connected between the high level voltage generator 44 and the second voltage line SVL.

The high level voltage generator 44 supplies a high level volta e VDD in the 9 shape of direct current maintaining a constant voltage level stably to the voltage controller 46. The voltage controller 46 alternately couples the second voltage line SVL 13 with the high level voltage generator 44 and the ground voltage line GVL, thereby -generating the high level gate voltage Vgh as shown in Fig. 7 at the second voltage line 01 __7 -1.) 0 SVL. To this end, the voltage controller 46 includes atwo-contact control switch 50 for responding to a gate scanning clock GSC. The two- contact control switch 50 connects the second voltage line SVL to the high level voltage generator 44 at a high logic region 17 0 11.) of the gate scanning clock GSC, so that a high level voltaore VDID emergres at the second IP C, voltage line SVL and the gate line GL.

I When the gate scanning clock GSC transits &om a high logic into a low looric, the two-contact control switch 50 connects the second voltage line SVT_ to a rround voltage 10 line GVL, thereby dropping a voltage at the second voltage line S'V'L and the gate line ZD GL from the high level VDID in the exponential function shape. At this time, the voltage at the second voltage line SVL and the -ate line GL is discharged into the around voltage 0 In line in accordance with a time constant of the parasitic resistor Rp and the parasitic capacitor Cp, thereby slowly changing the falling edges of the high level Gate voltacre 0 -CP I__') Vgh and the scanning signal SCS in an exponential function shape as shown in Fig. 7.

Accordingly, the TFT CTMN included in the pixel 311 is turned on until a voltage of the scanning signal SCS from the gate line GL drops less than its threshold voltage. At this time, an electric charge charged in a liquid crystal cell Clc is pumped into the gate line GL, but a sufficient electric charge is charged into the liquid crystal cell Clc by means of a data voltage signal DVS passing through the TIFT CTMN &om a signal line SL. Accordingly, the voltage charged in the liquid crystal cell Clc does not drop. Then, since a voltage variation amount in the gate line GL is a maximum threshold voltage of the TFT CNIN when a voltage of the scanning signal SCS at the gate line GL drops less than a threshold voltage of the TFT CNLN, electric charge amount pumped from the liquid 0 crystal cell Clc into the gate line GL becomes very small. As a result, a feed through volta-e )Vp can be suppressed sufficiently. Furthermore, a flicker and a residual image do not appear at a picture displayed with the pixel 3 1.

Fig. 8 shows a liquid crystal display apparatus according to a third embodiment of the present invention. The liquid crystal display apparatus of Fig. 8 has a circuit configuration similar to that of Fig. 6, except that a voltage controller 46 further includes a parallel connection of a resister R I and a capacitor C I between the two-contact control 14 switch 50 and the ground voltage line GVL. The resistor R1 and the capacitor C I increases a time constant when a voltage at a second voltage line SVL and a gate line GL C' is dischar, ed into the ground voltage line GVL. Accordingly, the falling edge of a high level orate voltage Vgh at the second voltage line SNTL has a slower slope than the rising I= - edcre thereof as shown in Fig. 9. Only one of resistor RI and capacitor C I may be used as needed. The failing edges of the high level orate voltage Vgh and the scanning signal lt 0 - Z:P SCS are controlled more slowly than the rising edges thereof as described above, so that the liquid crystal display apparatus can suppress a feed through voltage)Vp sufficiently and have a rapid response speed.

Referring now to Fig. 10, there is shown a liquid crystal display apparatus according to a fourth embodiment of the present invention. The iiquid crystal display apparatus of Fig. 10 has a circuit configuration similar to that of Fig. 6, except that a voltage controller 46 further includes a one-contact control switch 52 connected between the high level voltage generator 44 and the second voltage line SVL instead of the twocontact control switch 50, and a TFT MWN connected between the second voltage line SVL and the ground voltage line GVL. The one-contact control switch 52 and the TFT NN is complementarily turned on in accordance With a logical state of a gate scanning clock GSC. More specifically, the onecontact control switch 52 is turned on during an interval when the gate scanning clock GSC remains at a high logic; while the TFT NLN is turned on during an interval when the gate scanning clock GSC remains at a low logic.

The TFT MN provides a discharge path to the second voltage line SVL and the gate line GL with the aid of the orate scanning clock GSC, thereby changing the falling ed es of the high level gate voltage Vgh and the scanning signal SCS into an exponential 9 0 function shape. Also, the TFT MN increases a time constant with the aid of a resistor component and a capacitor component occurring upon its turning on, when voltages at a second voltage line SVL and a gate line GL are discharged into the ground voltage line GVL. Accordingly, the falling edge of the high level gate voltage Vah at the second voltage line SVL has a slower slope than the rising edge thereof as shown in Fig. 9. Also, the falling edge of the scanning signal SCS at the gate line GL changes more slowly than C the rising thereof as shown in Fig. 9. The falling edges of the high level gate voltage Vgh and the scanning signal SCS are controlled more slowly than the rising edges thereof as described above, so that the liquid crystal display apparatus can suppress a feed through voltage)Vp sufficiently and have a rapid response speed.

The TFT MN has a suitable channel width in such a manner that a resistance value of the resistor component and a capacitance value of the capacitor component are set appropriately. Furthermore, a resistor and/or a capacitor for slightly increasing a time constant may be added between the TFT MN and the ground voltage line GVL.

0 Z7 Fig. I I shows a liquid crystal display apparatus according to a fifth embodiment of the present invention. The liquid crystal display apparatus of Fig. I I has a circuit configuration similar to that of Fig. 10, except that a resistor R2, instead of the TFT NLN, is connected between the second voltage line SVL and the ground voltage line GVL. When a one-contact control switch 52 is turned on with the aid of a high logic of a gate scanning clock GSC, the resistor R2 prevents a leakage of voltage to be charged in the second voltage line SVL and a gate line GL. Otherwise, when the one-contact control switch 52 is turned off, the resistor R2 lengthens a time when voltages at the second voltage line SVL and the gate line GL are discharged into the ground voltage line GVL, thereby slowly changing the fafling edges of a high level gate voltage Vgh and a scanning signal SCS into an exponential function shape. In other words, the resistor R-1 increases a time constant of the second voltage line SVL and the gate line GL when the one- contact control switch 52 is turned on. Accordingly, the falling edge of the high level gate voltage Vgh at the second voltage line SVL has a slower slope than the rising edge thereof as shown in Fig. 9. Also, the falling edge of the scanning signal SCS at the gate line GL changes more slowly than the rising thereof as shown in Fig. 9. The filling edges of the high level gate voltage Vgh and the scanning signal SCS are controlled more slowly than the rising edges thereof as described above, so that the liquid crystal display apparatus can suppress a feed through voltage)Vp sufficiently and have a rapid response speed.

Moreover, in the liquid crystal display apparatus according to the embodiments of the present invention as shown in Fig. 6, Fig. 8, Fig. 10 and Fig. 11, the switching operation of the voltage controller 46 is controlled by the gate scanning clock GSC, so that the timing controller 48 in Fig. 5 can be eliminated. As a result, the circuit configuration of the liquid crystal display apparatuses according to the second to fifth 16 embodiments shown in Fig. 6, Fig. 8, Fig. 10 and Fig. I I can be still more simplified. Further, in the liquid crystal display apparatuses according to the second to fifth embodiments of the present invention, a duty cycle of the gate scanning clock has been expressed as 50%, but it may be controlled suitably in a range in which a voltage can be sufficiently charged in the liquid crystal cell.

Fig. 12 shows a scanning signal SCS and a data voltwze siznal DVS, each developed on gate line GL and signal line SL of the liquid crystal display apparatuses according to the first to fifth embodiments of the present 'Invention. The voltage level of the scanning signal SCS shown in Fig. 12 approaches to the voltage level of the data voltage signal DVS at the falling edge of the scanning signal SCS. Therefore, in the liquid crystal display apparatus according to the present invention, the feed through voltage)Vp can be suppressed and the response speed enhanced.

Fig. 13) illustrates a liquid crystal display apparatus according to a sixth embodiment of the present invention. The liquid crystal display apparatus of Fig. 13 includes a low level gate voltage generator 40 and a high level gate voltage generator 42, 1.7 - In each connected with a first voltage line FVL and a second voltage line SVL. The low level gate voltage generator 40 applies a low level gate voltage Vgl, maintaining a constant voltage level to a controlled switch 3)9 connected to the first voltage line FVL. The high level gate voltage generator 42 generates a pulse shape of a high level gate I Z-D 1- voltage Vgh, where a first high level voltage VDD I is alternated with a second high level voltage VDD2, as shown Fig. 14.

In order to generate the high level gate voltage Vah, the high level gate voltage generator 42 is composed of a high level voltage generator 54 for generating the first and second high level volta es VDD I and VDD2 and a voltage controller 56 connected 1 9 between the high level voltage generator 56 and the second voltage line SVL.

The first high level voltage VDD I generated in the high level voltage generator 1 1 54 maintains stably a constant voltage level, and the second high level voltage VDD2 has I a constant voltage level between the first high level voltage and the low level gate voltage D Vgl. The first and second high level voltages VDD I and VDD2 are applied to the -30 voltage controller 56. The voltage controller 56 supplies, altematively, the first and 17 second high level voltages to the second voltage line SVL, such that the high level gate voltage Vah, as shown in Fig. 14, is developed on the second voltacre line S'V'L.

W -D The voltage controller 56 includes a second controlled switch 58 responding to a gate scanning clock GSC. During the high logic period of the gate scanning clock GSC, 1:1 CP Z: - the second controlled switch 58 supplies the first high level voltage %, !)D I to the second voltage line SVL, thereby appearing the First high level voltage'Vah on the second voltage line SVL. In the other hand, the second controlled switch 58 applies the second high level voltacre VDD2 to the second voltage line S/l to develop the second high level voltage VDD2 on the second voltacre line S'vl, at the low logic period of the grate scanning clock GSC. As a result, the high level crate voltage Vah has, sequentially, the _-:- ZID first and second high level voltages VDDI and VDD2, every period of the -ate scanning C) clock GSC.

In the liquid crystal display apparatus of Fig. 13, there is included a gate driver 3) 4 for driving gate lines GL on the liquid crystal panel 30. The liquid crystal panel 330 has pixels 3 1, each connected with the signal line SL and the gate line. Each of the pixels 3) I consists of a liquid crystal cell Clc for controlling a amount of lights passed through, its own responding to the data voltage signal DVS from the signal line SL, and a TFT for responding to the scanning signal SCS to switch the data voltage signal DVS to be supplied to the liquid crystal cell Clc. In the pixel, an additional capacitor Cst is also connected with the liquid crystal cells Clc in the parallel.

The gate driver 3 34 is composed of a shift register cell 36A for responding to a 0 Pte start pulse GSP from a control line CL and the crate scanning clock GSC from the gate clock line GCL, and a first controlled switch _3 3 9 connected between the shift register cell 36A and the gate line GLI. The shift register cell 36A outputs the gate start pulse GSP to its output terminal QT at the raising edge of the gate scanning clock GSC. Then, in the gate line GL 1, there is developed a scanning signal SCS having the low level gate voltage Vg1 or the high level gate voltage Vgh. In detail, the first controlled switch 39 applies, sequentially, the first and second high level voltages VDD I and VDD2 during the high logic period of the output signal ftom the shift register cell 3 3 9A, and applies the low level gate voltage Vg1 to the gate line GL I when output signals of the shift register cell 336Ago tothe low logic. Asa result, the scanning signal, as shown in Fig... 14,varied 18 in a stepwise shape, is generated on the gate line GLL ASCSn showsawave form ofa 0 scanning signal to be applied to a next gate line.

Since the scanning signal SCS is varied in a stepwise fashion, the TFT Cv is turned off when the voltage of the scanning signal from the gate line GL I drops into a ID voltacye level lower than its threshold voltage. Then, although the charges in the liquid crystal cell Clc included in the pixel 3 1 are pumped toward the gate line GL 1, the fully charged are charged in the liquid crystal cell Clc by the data voltage signal DVS from the 17 =1 Z sicynal line SL throu h the TFT C,'vC,;. Therefore, a voltace charged in the liquid crystal 9 cell Clc is not decreased. In the case where high level gate voltage Vgh drops below the - the charge is pumped ftom the liquid crystal cell to threshold voltage of the TFT OWNI 1.2 the gate line GL I because a maximum value of a voltage variation on the gate line GL I becomes the threshold voltage of the TFT Ci\4N-. As a result, the feed through voltage )Vp is fully suppressed; furthermore, a flicker and residual image doesn't appear on a picture point displayed by the pixel 3) 1.

In Fig. 0, the parasitic resistor Rp and the parasitic capacitor Cp, as shown in Fig.

5, exist on the gate line GL I and affect the high level gate voltage Vgh but have been eliminated fi7om the drawing for brevity.

Fig. 15 shows a scanning signal SCS and a data voltage signal DVS, each developed on gate line GL and signal line SL of the liquid crystal display apparatus, according to the sixth embodiment of the present invention. The failing edge of the scanning signal SCS changes in the shape of a linear function. The voltage level of the scanning signal SCS, shown in Fig. 15, approaches to the voltage level of the data voltage signal DVS at the falling edge of the scanning signal SCS. Therefore, in the liquid crystal display apparatus according to the present invention, the feed through voltage)Vp can be suppressed and the response speed is enhanced.

Fig. 16 illustrates another embodiment of the voltage controller 56 as shown in Fig. 1-3. The voltage controller 56 of Fig. 16 includes a comparator 60 for receiving the gate scanning clock GSC to its invert terminal "-" through a resistor R3, and first and second transistors Q I and Q2 for responding complimentarily to the output signal of the comparator 60. The comparator 60 compares a reference voltage Vref from a variable 19 resistor VR with the gate scanning clock GSC as shown in Fig. 17, and generates a comparison signal having a logic state according to a comparison resultant.

The comparator 60 applies a low logic of the comparison signal to the base terminals of the first and second transistors Q I and Q2, in case the reference voltage Vref is higher than the crate scannino, clock GSC. On the other hand, if the reference sianal is lower than the crate scanning clock GSC, the comparator 60 supplies a high logic of the comparison signal to the base terminals of the first and second transistors Q I and Q2.

Then, the reference voltage Vref from the variable resistor VR divides a voltage difference between the first or second high level voltage 'vl)D I or VIDD2 and a crround voltage GINTE), and applies the divided voltage to the non-invert terminal "+" of the comparator 60 as the reference voltage Vref The first transistor Q1 applies the first high level voltage VDD I from the high level voltage generator 54 of Fig. I') to the second voltage line SVL, during the high logic period of the comparison signal from the comparator 60, while the second transistor Q2 supplies the second high level voltage VDD2 from the high level voltage generator 54 to the second voltage line S'VI in the low 111 ID logic interval of the comparison signal from the comparator 60.

Therefore, on the second voltage line SVL, is developed the high level Crate voltage signal Vgh, varying in the complementary with the gate scanning clock GSC, as shown in Fig. 17. The high level crate voltage Vgh has, alternatively, the first and second hi h level voltages VDD I and VDD2 in response with the gate scanning clock GSC.

9 Also, the high level gate voltage Vgh is used to a liquid crystal display apparatus, which the shift register cell 36A is to the falling edge of the gate scanning clock GSC.

Furthermore, the high level gate voltage Vgh has an equal shape with the gate scanning clock GSC; in case these are changed, the first and second transistors Q I and Q2 or the reference voltage and the crate scanning clock GSC are to be each applied to the invert and non-invert terminals and "+" of the comparator 60. Meanwhile, a resistor R4, connected between the second voltage line SVT_ and the invert terminal "- " of the comparator 60, feeds back a voltage on the second voltage line SVL to the invert terminal of the comparator 60, such that the high level -ate voltage Vgh responds rapidly to the gate scanning clock GSC.

Referring to Fig. 18, there is shown a liquid crystal display apparatus according to a seventh embodiment of the present invention that includes a data driver 32 for driving signal lines SLI to SLm on a liquid crystal panel 30, and a crate driver 34 for driving crate lines GLI to GLn on the liquid crystal panel 30. In the liquid crystal panel 30, pixels 31 connected to signal lines SL and gate lines GL are arranged in an active matnx pattern.

Each pixel '31 includes a liquid crystal cell Clc for responding to a data voltage signal CP DVS from the signal line SL to control a transmitted light quantity, and a thin film transistor(TFT) CNTfN for respondinc, to a scannin si2nal SCS from the crate line GL to switch the data voltage signal DVS to be applied &om the signal line SL to the liquid crystal cell Clc.

Each pixel 311 has a support capacitor Cst connected, in parallel, to the liquid crystal cell Cic. This support capacitor Cst serve to buff a voltage charged in the liquid crystal cell Clc. As the gate lines GL I to GLn are sequentially driven, the data driver 32 applies the data voltacre signal DVS to all the signal lines SL I to SLm. The crate driver C) C= 1-:1 1= '34 allows the gate lines GL I to GLn to be sequentially enabled for each horizontal synchronous interval by applying the scanning signal SCS to the gate lines GL I to GLn sequentially.

The gate driver 34 has a shift register 336 responding to a crate start pulse GSP C from a control line CL and a crate scanning clock GSC from a -ate clock line GCL, and a level shifter 62 connected between the shift register 33 6 and the crate lines GL I to GLn.

The shift register.3) 6 outputs the gate start pulse GSP from the control line CL to one of n output terminals QT I to QTn and, at the same time, responds to the gate scanruing clock GSC to shift the gate start pulse GSP from the first output terminal QT I to the nth output terminal QTn, sequentially. Also, the shift register 36 operates at an integrated circuit driving voltage VCC having 5 V, corresponding to a logical voltage level.

The level shifter 62 generates n scanning signals SCS by shifting voltage levels of the output signals of the shift register '36. To this end, the level shifter 62 includes n PMOS transistors NP1 to NTn connected commonly to a first voltage line FVL, and n NMOS transistors MNI to NLNn connected commonly to a second voltage line SVL. The " 1 first voltage line FVL receives a low level gate voltage Vg1 from a low level crate voltage generator 40. The n PMOS transistors W I to NlPn are connected to the gate lines GL I 21 to GLn, respectively. Also, the n PMOS transistors MI? I to TWn have gate electrodes each connected to the n output terminals QT I to QTn of the shift re, ister 3)6, respectively. Similarly, the n NTMOS transistors N1NI to ND;n are coupled to the gate lines GL I to GLn, respectively. Also, the n N'I'VfOS transistors '.vLN,- I to Nn have gate electrodes, each connected to the n output terminals QTI to QTn of the shift register 336, respectively. Each PMOS transistor MP I to TMPn responds to a signal ftom the respective output terminal QTI to QTn of the shift register 36 to be turned on in the complement to each Z:> N-TVIOS transistors MNI to MNn.

The first to nth PMOS transistors MW I to VMn, each responding to the signals from the n output terminals QTI to QTn of the shift register 36, are sequentially tumed off by one horizontal synchronous period. Accordingly, the second voltage line SVL is sequentially connected to the n gate lines GL I to GLn by one horizontal synchronous period. The gate driver 34 also has n PMOS transistors NPn+1 to TW2n, connected in parallel between the second voltage line SVL and a high!evel voltage generator 44, and a discharging resistor Rd connected between a ground line GNIDL and the second voltage line SVL.

The n PMOS transistors MPn+ I to MP2n, which are voltage controllers, respond commonly to a gate output enable signal GOE, as shown in Fig. 19, on an enable line EOL, thereby being turned on during a period from the start point to the middle point of C C) the horizontal synchronous period. When the n PMOS transistors Wn+l to MP2n are turned on, the high level voltage VDD generated at the high level voltage generator 44 is applied to any one of the n NMOS transistors MNI td'NLNn via a parallel circuit of the n PMOS transistors WIn+l to MP2n and the second voltage line SVL.

Meanwhile, if the n PMOS transistors MPn+l to MP2n are turned off, the voltage 25 charged in any one of the n -ate lines GL I to GLn is discharged into the ground line 0 ZD GNDL through the second voltage line SVL and the discharging resistor Rd. At the time, a discharging speed (a time constant) of the voltage on the gate line GL is determined by the discharging resistor Rd, a parasitic resistor Rc on the gate line GL and a parasitic 0 capacitor Cc on the gate line GL. Therefore, there is generated a high level gate voltage 0 C-D Vgh at the second voltage line SVL. The high level gate voltage Va I _-,h maintains the high level voltage VDD in the high logic interval of the gate scanning clock GSC (i.e., the 0 22 front half of the horizontal synchronous signal HS) and drops down gradually from the high level voltage VDD in a shape of exponential function, as shown in Fig. 19.

The first to nth crate lines GL 1 to GLn receive the high level crate voltacre Vgh on 0 Z - the second voltage line SVL through the respective MVIOS transistors NM I to NLN-n during one period of the horizontal synchronous signal HS and input the low level 0ate voltage VgI on the first voltage line FVL via the respective PMOS transistors 'VIP I to iv[Pn during a rest period. Consequently, the first to nth crate lines GL I to GLn receive scanning signals SCSI to SCSn as shown in Fig. 19, respectively. The scanning signal SCS maintains the high level voltage VDD in the high logic interval of the crate scanning 17 Z.) clock GSC (Le., the front half of the horizontal synchronous signal HS) and decreases slowly from the high level voltage VDD to the voltage approaching to a threshold voltage of the TFT CMN on the liquid crystal panel 30 In the exponential function shape. Also, the scanning signal SCS drops down rapidly into the voltage (i.e., the low level gate voltage Vgl) lower than the threshold voltage of the TFT CTMN. As described above, since the falling edge of the scanning signal SCS applied to the crate line GL of the liquid crystal panel.3)0 changes gradually, the TFT ONN included in the pixel 3 1 is turned on until a voltage of the scanning signal SCS from the -ate line GL drops less than its threshold voltage.

At this time, electric charge charged in a liquid crystal cell Clc is pumped into the crate line GL. However, sufficient electric charcre is charged into the liquid crystal cell 1) -17 Clc by means of a data voltage signal DVS passing through the TFT CNUS; from a signal line SL. Accordingly, the voltage charged in the liquid crystal cell Clc does not decrease.

Since a voltage variation amount in the gate line GL is a maximum threshold voltage of the TFT CTININ when a voltage of the scanning signal SCS at the crate line GL drops less than a threshold voltage of the TFT CNIEN, electric charge amount pumped from the liquid crystal cell Clc into the gate line GL becomes very small. As a result, a feed through voltage)Vp can be suppressed sufficiently. Further, the n PMOS transistors TWn+1 to NV2n lower a value of resistance between the second voltage line SVL and the hiah level voltaite izenerator 44 in order to minimize an attenuation of the hlah level -30 voltage VDD to be applied from the high level voltage generator 44 to the second voltage line SVL.

23 Accordingly, n-l PMOS transistors of the n PMOS transistors MPn+1 to TW2n can be eliminated. In this case, the gate driver 34 is simplified in a circuit configuration. Furthermore, the gate start pulse GSP, the gate scanning clock GSC and the -ate enable 11) C 17 signal GOE are generated at a timing controller (not shown).

Fig. 20 shows a line scanning circuit for driving any one of the -ate lines included ID - 0 in the active matrix liquid crystal display apparatus of Fig. 18. The line scanning-ircui it of Fig. 20 includes a gate driver 34 for driving a gate line GL on a liquid crystal panel 30. The liquid crystal panel 30 includes a pixel 3 1 connected to a signal line SL and the cyate line GL. The pixel 3) 1 includes a liquid crystal cell Clc for responding to a data voltage signal DVS from the signal line SL to control a transmitted light quantity, and a TFT CMIN for responding to a scanning signal SCS &om the gate line GL to switch the data voltage signal DVS to be applied from the signal line SL to the liquid crystal cell Cle.

Also, the pixel -3)1 has a support capacitor Cst connected, in parallel, to the liquid crystal cell Clc.

The gate driver 34 consists of a shift register cell 36A responding to a gate start IP 0 pulse GSP from a control line CL and a gate scanning clock GSC from a - ate clock line GCL, and a level shifter cell 62A connected between the shift register cell 36A and the gate line GL. The shift register cell 36A outputs the gate start pulse GSP as shown in Fig 0 0' 19 at the rising edge of the gate scanning clock GSC as shown in Fig. 19 to an output CP terminal QT.

The level shifter 62A generates a scanning signal SCS by shifting voltage level of I Z 0 - the output signal of the shift register cell 336A. To this end, the level shifter cell 62A includes a first PMOS transistor NO I connected between a first voltage line FVL and a gate line GL on the liquid crystal panel 30, and a first NMOS transistor MNI connected between a second voltage line SVL and the gate line GL. The first voltage line FVL receives a low level gate voltage 'Vgcl from a low level gate voltage generator 40. The PMOS transistor 1W I has a gate electrode connected to an output terminal QT of the shift register cell 36A. Similarly, the first N-MOS transistor WN1 has a gate electrode _connected to the output terminal QT of the shift register cell 36A. The first NMOS transistor MNI responds to a signal from the output terniinal QT of the shift register cell 36A to be tumed on during an arbitrary horizontal synchronous period of a frame interval.

24 The first PMO S transistor NT I responding to the signal from the output terminal QT of the shift register cell -336A is turried-on during one frame interval, except the arbitrary horizontal synchronous period.Accordingly, the second voltage line SVL is connected to the gate line GL only during the arbitrary horizontal synchronous period, and the first voltage line FVL is coupled to the gate line GL during the frame interval, except the arbitrary horizontal synchronous period- The level shifter cell 62A also has a second PMOS transistor iVEP2 connected between the second voltage line SVL and a high level voltasze Zenerator 44, and a discharging resistor Rd connected between a around line GNT-DL and the second voltage line SVL. The second PMOS transistor NIP2 responds to a gate output enable signal GOE, as shown in Fig. 19, on an enable line EOL, thereby being, turned on during the period fTom the start point to the middle point of the horizontal synchronous period. When the second PMOS transistor NP2 is turned on, the high level voltage VDD generated at the high level voltage generator 44 is applied to the first NMMOS transistor Nf,;l via the second PMOS transistor NT2 and the second voltage line SVL. On the other hand, in the case where the second PMOS transistor MP2 is turned off, the voltage charged in the gate lines GL is discharged into the ground line GN-DL through the second voltage line SVL and the discharging resistor Rd.

A discharging speed (a time constant) of the voltage on the gate line GL is determined by the discharging resistor Rd, a parasitic resistor Rc on the gate line GL and a parasitic capacitor Cc on the gate line GL. Therefore, there is generated a high level gate voltage Vgh at the second voltage line SVL. The high level gate voltage Vah maintains the high level voltage VDD in the high logic interval of the gate scanning clock GSC (i. e., the front half of the horizontal synchronous signal HS) and drops down gradually from the high level voltage VDD in a shape of exponential function, as shown in Fig. 19. The gate line GL receives the high level gate voltage C g Vgh on the second voltage line SVL through the first,NMOS transistor NTMI during the arbitrary horizontal I synchronous period and inputs the low level gate voltage VgI on the first voltage line 0 1-:1 FVL via the first PMOS transistor W, I during the ftame interval, except the arbitrary 3)0 horizontal synchronous period.

Consequently, the gate line GL receives any one of scanning signals SCSI to SCSn as shown in Fig. 19. The scanning signal SCS maintains the high level volta e 9 VDD in the high logic interval of the gate scanning clock GSC (i.e., the front half of the a horizontal synchronous signal HS) and decreases slowly t-rom the high level voltagre VDD to the voltage approaching to a threshold voltage of the TFT CNIN on the liquid crystal panel 30 in the exponential function shape. Also, the scanning signal SCS drops I Z down rapidly into the voltage (i.e., the low level gate voltage Vorl) lower than the threshold voltage of the TFT CNLN.

As described above, since the falling edge of the scanning signal SCS applied to the grate line GL of the liquid crystal panel 30 changes gradually, the TFT C.M.N- included in the pixel I is turned on until a voltage of the scanning signal SCS from the gate line GL drops less than its threshold voltage.

At this time, an electric charge charg ged in a liquid crystal cell Clc is pumped into the gate line GL. However, sufficient electric charge is charged into the liquid crystal -7 1 0 C) cell CIc by means of a data voltage signal DVS passing through the TFT CMIN from a signal line SL. Accordingly, the voltage charged in the liquid crystal cell Clc does not drop down. Then, since a voltage variation amount in the gate line GL is a maximum threshold voltage of the TFT CN2; when a voltage of the scanning signal SCS at the gate line GL drops less than a threshold voltage of the TFT CMN-, the electric charge amount pumped from the liquid crystal cell Clc into the gate line GL becomes very small. As a result, a feed through voltage Vp can be suppressed sufficiently.

Fig. 21 illustrates an active matrix liquid crystal display apparatus according to an eighth embodiment of the present invention. The liquid crystal display apparatus of Fig. 21 has a circuit configuration similar to that of Fig. 18, except that a voltage controller 64,is connected between the second voltage line SVL and the high level voltage generator 44 instead of the n PMOS transistors NTn+ I to NT2n connected between the second voltage line SVL and the high level voltage generator 44 and the discharging resistor Rd connected between the second voltage line SVL and the ground line GNDL. The voltage controller 64 responds to a gate scanning clock GSC from the gate clock line GSL to connect the high level voltage generator 44 to the second voltage line SVL or to provide a discharging path to the second voltage line SVL. The voltage controller 64 transmits the 26 high level voltage VDD from the high level voltage generator 44 to any one of the gate lines GLI to GLn viathe second voltage line SVL and anyone ofthe n WIT OS transistors MNI to MNn when the scanning clock GSC has a high logic value.

When the crate scannina clock GSC Coes to a low locric value, the voltacre 0 W W 1:1 controller 64 provides the discharging path to the second voltage!lne PV1, thereby discharging a voltage charged in any one of the gate lines GL 1 to GLn into the 1:1 17 discharging path via the second voltage line SVL. At the time, a discharging speed (a w 1:7 = time constant) of the voltage on the crate line GL is determined by the resistance value of the discharging path, a parasitic resistor Rc on the gate line GL and a parasitic capacitor 1 w Cc on the gate line GL. Consequently, the voltage controller 64 generates a high level crate voltage Vgh at the second voltage line SVL. The high level crate voltage Vgh maintains the high level voltage VDD in the high logic interval of the gate scanning clock GSC (i.e., the front half of the horizontal synchronous signal HS) and drops down gradually from the high level voltage VDD in a shape of exponential function, as shown in Fig. 19.

The first to nth crate lines GLI. to GLn receive the hiah level crate voltage Vah on 0 C1 the second voltage line SVL through the respective NIMOS transistors MINI to ILNri during one period of the horizontal synchronous signal HS. Also, each crate line GL 1 to GLn inputs the low level crate voltage Val on the first voltage line F-Y'L via the respective PMOS transistors 1W I to NTn during the ftame interval, except one horizontal synchronous penod.

Therefore, the first to nth gate lines GL 1 to GLn receive scanning signals SC S 1 to SCSn, as shown in Fig. 19, respectively. The scanning signal SCS maintains the high level voltage VDD in the high logic interval of the gate scanning clock GSC (i.e., the front half of the horizontal synchronous signal HS) and decreases slowly from the high level voltac, e VDD to the voltage approaching to a threshold voltage of the TFT Ci'v on 0 the liquid crystal panel 30 in the exponential function shape. Also, the scanning signal SC S drops down rapidly into the volta e (i.e., the low level crate voltage Vg1) lower than 9 "W the threshold voltage of the TFT CMN. As descr-ibed above, since the falling edge of the 1 scanning signal SCS applied to the gate line GL of the liquid crystal panel 30 changes 27 gradually, the TFT CMN included in the pixel 31 is turned on until a voltage of the scanning signal SCS from the gate line GL drops less than its threshold voltage.

At this time, electric charge charged in a liquid crystal cell Cle is pumped into the aate line GL. However, sufficient electric charge is charged into the liquid crystal cell Clc by means of a data voltage signal DVS passing through the TFT C,\/LN &om a signal line SL. Accordingly, the voltage charged in the liquid crystal cell Cic does not drop down. Then, since a voltage variation amount in the gate line GL is a maximum threshold voltage of the TFT CDvL\ when a voltage of the scanning signal SCS at the gate line GL drops less than a threshold voltage of the TFT Ci'v, an electric chara ge amount pumped from the liquid crystal cell Clc into the gate line GL becomes very small. As a result, a feed through voltage Vp can be suppressed sufficiently.

Fig. 22A shows a waveform of a scanning signal generated by the active matrix liquid crystal display apparatus according to the present invention. Fig. 22B depicts a Z:1 waveform of a scanffing signal provided by the conventional active matrix liquid crystal display apparatus. The scanning signal has a falling edge decreasing gradually in a shape of exponential function and differing to that of the scanning signal as shown in Fig. 22B.

Consequently, the active matrix liquid crystal display apparatus according to the present invention reduces a potential difference between the gate and source electrodes of the TFT CMN when the TFT CMN is turned off. Also, an electric charge amount discharged from the liquid crystal cell Clc becomes very small. As a result, a feed through voltage Vp can be suppressed sufficiently. Further, a flicker is substantially reduced.

Fig. 23A shows a current variation on any one of gate lines GL when the active matrix liquid crystal display apparatus according to the present invention drives the TFT CMN. Fig. 23B depicts a current variation on any one of gate lines GL when the conventional active matrix liquid crystal display apparatus drives the TFT CMN.

Referring to Figs. 23A and 23B, an overshoot noise component 102 is greatly suppressed by means of the active matrix liquid crystal display apparatus according to the present invention.

Fig. 24 illustrates in detail an embodiment of the voltage controller 64 shown in Fig. 2 1. The voltage controller 64 of Fig. 24 includes a first and a second resistor R 1 and R2 connected in series between a high level voltage line VDDL and a ground line GNDL, 28 and a third resistor R3 connected between a first node NI and a second voltage line SVL. The first and second resistors RI and R2 divide a high level voltage VDD on the high level voltage line VDDL, thereby emerging a divided voltage at the first node NI. The third resistor R3 limits a quantity of current between the first node NI and the second 5 voltage line SVL.

The voltage controller 64 further includes a first transistor TRI connected between the first node NI and a second node N2, a second transistor TR2 connected between the second resistor R2 and the ground line GNDL The first transistor TRI responds to a voltage on the second node X2 and transmits selectively the high level voltage on the high level voltage line VDDL toward the first node NI. In detail, the first transistor TRI is turned on when the volta.e on the second node N2 is in a voltage below I:, g its threshold voltage (i.e., 0.7V), so as to allow the voltage on the first node NI to maintain the high level voltage VDD. Meanwhile, if the voltage on the second node XL2 is in a voltage above the threshold voltage of the transistor TR, the first transistor TR1 is turned off to open a current path between the first node NI and the high level voltage line VDDL The first transistor TR I employs a junction transistor of P-type. The voltage on the second node N2 is varied with an operating state of a third transistor TR3 having a base electrode connected to a fourth node N4. The third transistor TR3 is turned on when a gate scanning clock GSC on the fourth node N14 has a high logic value, thereby forming a current path which proceeds from the high level voltage line VDDL to the ground line GNDL through a fourth resistor R4, the second node N2, and its emitter and collector electrodes.

In this case, there is developed the voltage lower than the threshold voltage of the transistor TR at the second node N2. On the other hand, if the gate scanning clock GSC on the fourth node N4 is in a low logic value, the third transistor TR3 is turned off, such that the high level voltage is deveioped on the second node N2. Meanwhile, the second transistor TR2 responds to the voltage on the third node N3) to connect selectively the second resistor R2 to the ground line GNDL In detail, the second transistor TR2 connects the second resistor R27 to the ground line GNDL when the voltage on the third node N3 is higher than its threshold voltage. At this time, the voltage on the second voltage line SVL is discharged into the ground line GNDL via the third resistor R3, the 29 first node NI, the second resistor R2, and its collector and emitter electrodes. Meanwhile, if the voltage on the third node N3) is lower than the threshold voltage of the second transistor TR2, the second transistor TR3 opens the second resistor R2 from the ground line GNDL The second transistor TR2 employs a junction transistor of N-type. The voltage on the third node N33 is varied with an operating status of a fourth transistor TR4 having a base electrode connected to the fourth node N4. The fourth transistor TR4 is turned on when the gate scanning clock GSC &orn the fourth node N4 has the high logic value, thereby connecting the third node N3) to the ground line GNiDL. Thus, the ground 0 C) Z> voltage GND emerges on the third node N3). On the other hand, if the crate scanning clock GSC on the fourth node N4 has a high logic value, the fourth transistor TR4 is turned offto charge the high level voltage VD1) on the high level voltage line YDDL into the third node N-33 via the third resistor R3.

Consequently, the voltage on the second node N2 varies in the same shape to that on the third node N3. Since the voltages on the second and third nodes N2 and N13) have the same shape, the first and second transistors TRI and TR2 are alternatively driven. In other words, The first transistor TRI is turned in the high logic interval of the gate 0 W scanning clock GSC and the second transistor TR2 in the low lo 'c interval of the crate p 11-15 scanning clock GSC. Accordingly, the voltages on the first node NI and the second voltage line SVL are equal to the high level voltage VDD in the high level interval of the gate scanning clock GSC and decrease in exponential function shape from the high level voltage VDD to the divided voltage level. As a result, a high level gate voltag ge Vgh having a waveform is generated as shown in Fig. 19 on the second voltage line SVL.

The gate scanning clock GSC is applied from the crate clock line GCL to the fourth node N4 through a seventh resistor R7. The seventh resistor R7 limits a quantity of current flowing from the gate clock line GCL to the fourth node N4 via the seventh resistor R7. The second and third resistors R2 and R3 determine discharging speed of the voltage on the gate line GL together with a parasitic resistor Re and a parasitic capacitor Cc existing on the gate line GL which is connected to the second voltage line SVL.

Fig. 25 shows a tab type of liquid crystal display apparatus according to the present invention. In the tab type of the liquid crystal display apparatus shown in Fig. 25, a liquid crystal panel 30 is provided with a liquid crystal layer 30C sealed between an upper glass substrate -330A and a lower glass substrate 3)OB. The liquid crystal panel 30 is connected with a PCB (Printed Circuit Board) module 68 by a FPC (Flexible Printed Circuit) film 66. The PCB module 68 has a control circuit 72, a low level gate voltage crenerator 40 and a high level crate voltage generator 42 on a PCB 70. The FPC film 66 has one end connected with the pad area of the lower glass substrate.)OB, and another end coupled with the edge of the undersurface of the PCB 70. In the intermediate portion of the FPC film 66, date drivers 332 and/or gate drivers 34 are installed, The data drivers 32 and/or the crate drivers '34 are connected with the liquid crystal panel 30 and the PCB module 68 by the FPC film 66. The FPC film 66 has a first conductive layer pattern 67A connecting the liquid crystal panel 3)0 with the data drivers 3 2 and/or the gate drivers 34, and a second conductive layer pattern 67B coupling electrically the data drivers 32 and/or the gate drivers 3)4 and the PCB module 68. The first and second conductive layer patterns 67A and 67B are each surrounded with first and second protective films 69A and 69B in such a manner that both ends of the first and second conductive layer patterns 67A and 67B are exposed, too.

Fig. 26 shows a COG (Chips On Glass) type of liquid crystal display apparatus according to the present invention. In the COG type of the liquid crystal display apparatus shown in Fig. 26, a liquid crystal panel '30 is provided with a liquid crystal layer 30C sealed between an upper glass substrate 3)OA and a lower glass substrate 30B.

The liquid crystal panel 30 is connected with a PCB module 68 by a FPC film 66. The PCB module 68 has a control circuit 72, a low level gate voltage generator 40 and a high level gate voltage generator 42 loaded thereon. Data drivers -3)2 and/or gate drivers 34 are mounted on the pad area of the lower glass substrate 30B. The data drivers 32 and/or the gate drivers 34 are connected with the PCB module 68 by the FPC film 66. The FPC film 66 connects the PCB module 68 with the liquid crystal panel -3)0, loading with the data drivers 3 32 and/or the gate drivers.334 thereon. The FPC film 62 has one end connected with the pad area of the lower glass substrate 3)OB, and another end coupled with the edge of the under surface of the PCB 70. The FPC film 66 has a conductive layer pattern 67 connecting electrically the liquid crystal panel 30 with the PCB module 31 68. The conductive layer pattern 67 is surrounded with a protective film 69 in such a manner that both ends of the conductive layer pattern 67 are exposed, too.

The low level gate voltage generator and the high level gate voltage generator included in the present invention are located on the PCB module and the voltage controller can be arranged on the LCD module in various pattern, Firstly, the voltage controller is installed on the PCB module. In other words, the high level gate voltage generator, the low level gate voltage generator and the voltage controller are arranged on the PCB module. When such a circuit configuration is used for the LC1) apparatus, the conventional gate driver IC also can be smooth the failing edge of the gate pulse.

Consequently, the object of the present invention can be accomplished without modifying the gate driver IC.

Secondly, the voltage controller is inserted into the gate driver IC. The voltage controller included in the ate driver IC can be formed the high level gate voltage 9 ZY 0 generator and the buffer as shown in Fig. 18. On the other hand, the voltage controller included in the gate driver IC can be connected between the high level gate voltage generator and a plurality of buffers. The gate driver IC including the voltage controller allows the LCI) module to have a small number of elements relative to the LCD module having the voltage controller arranged on the PCB module. Also, the gate driver having the voltage controller enables the cost of element to decrease.

As described above, in the liquid crystal display apparatus according to the present invention, a high level gate voltage is supplied to the level shifter of the gate dnver in the alternating current shape, thereby changing the falling edge of the scanning signal into any one of the linear, exponential or ramp function shapes. Accordingly, the liquid crystal display apparatus according to the present invention is capable of suppressing the feed through voltage Vp sufficiently, as well as preventing an occurrence of a flicker and a residual image. Furthermore, the liquid crystal display apparatus according to the present invention has a very simplified circuit configuration.

Moreover, in the liquid crystal display apparatus according to the present invention, the falling edge of the high level gate voltage has a slower slope than the rising edge thereof, thereby changing the falling edge of the scanning signal to be applied to the gate line more slowly than the rising edge thereof Accordingly, the liquid crystal display 32 apparatus according to the present invention is capable of preventing an occurrence of a flicker and a residual image as well as providing a rapid response speed.

Although the present invention has been explained by the embodiments shown in the drawings hereiribefore, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments but, rather than that, various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.

33

Claims

Claims:

I A liquid crystal display apparatus, comprising: a plurality of pixels including switching transistors, each switching transistor having an electrode connected to a pixel electrode and a gate electrode-, a plurality of data signal lines connected to the electrode associated with any one of the transistors; a plurality of gate signal lines connected to the gate electrode associated with any one of the transistors; and a aate driver connected to the plurality of -ate signal lines, the gate driver 0 -D M 1:0 receiving first and second voltages and outputting at least one of the First and second voltages in such a manner to sequentially drive the gate signal lines, the first voltage changing prior to driving successive gate signal lines, wherein the gate driver includes: a shift register for generating scanning signals to be applied respectively to the gate lines, wherein the shift register is responsive to a gate scanning clock; a level shifter making use of the first and second voltages to generate each anals- and voltage level of the scanning sig I a voltage controller for changing the first voltage applied to the level shifter prior to disabling of the scanning signals- 2. The liquid crystal display apparatus of claim 1, wherein the first voltage decreases prior to driving of the siccessive gate signal lines.

1 3. The liquid crystal display apparatus of claim 1, wherein the first voltage decreases exponentially.

4. The liquid crystal display apparatus of claim 1, wherein the first voltage decreases linearly.

5. The liquid crystal display apparatus of claim 1, wherein the first voltage is stepwisely decreased.

34 6. The liquid crystal display apparatus of any preceding claim, wherein a minimum value of the first voltage is higher than a maximum value of the second volta2e.

7. The lIquid crystal display apparatus of any preceding claim, wherein the voltage controller includes:

a switch for cutting off the first voltage applied to the level shifter prior to disafing ofthe scanning signal,. and a discharging path provided to the leve! during penod in which the scanning signal is cut off by mearis of the switch.

8. The Liquid crystal display appararis of claim 7, wherein the switch and the shift eaister respond to the gate scanning clock.

9. The Equid crystal display apparatus of claim 7, fui-ther corripr-isine, a timinR controller for controlling the switch.

10, The liquid crystal display apparatus of any of claims 1 to 9, wherein the voltage controller includes. an input tem-iinal for receiving the first volta---- 0 - 1 a first resistor connected between the input terminal and an input port of the level SE1fter-1 a first control switch and a second resistor connected in series berween the input porT of the level shifier and a ground voltage line, and a second control switch connected in parallel to the first resistor, the second control switch being driven alternatively with the first control switch- 11 The liquid crystal display apparatus of any preceding claim, wherein 1 -7 the shift register and the lever shifter are fabricated to include in an integrated circuit chip 12. The liquid crystal display apparatus of any preceding claim, wherein the shift register, the voltage controller and the level shifter are fabricated to include 0 in an integrated circuit chip.

0 13. The liquid crystal display apparatus of any of claims 1 to 6, wherein the voltage controller comprises a switch responsive to a crate output enable signal and 0 is connected between the first voltage and the level shifter.

14. The liquid crystal display apparatus of claim 13), wherein the gate output enable signal is inverse of the crate scanning clock.

0 Is. A method of driving a liquid crystal display apparatus includin pixels positioned at intersecting points of gate lines with signal lines and having thin film transistors connected to the gate I.ines and the signal lines, and a gate driver connected to the gate line and having a shift register, the method comprising the steps of inputting a first voltage and a periodically changing second voltage; supplying the second voltage, via a switching device, to the gate line; and supplying the first voltage, via the switching device, to the gate line, the switching device being controlled by the shift register, wherein a minimum value of the second 0 voltage is higher than a maximum value of the first voltage.

16. The method of claim 15, wherein the first voltage is supplied to the gate line during a time interval when the thin Elm transistors connected to the crate lines are turned on.

17- The method of claim 15 or 16, wherein the shift register receives a driving voltage corresponding to a logical voltage level- is. A method of manufactunrig a liquid crystal display apparatus, the method comprising the steps of 36 providing a plurality of pixels including switching transistors, each switching transistor having an electrode connected to a pixel electrode and a gate electrode; providing a plurality of data signal lines connected to the electrode associated with any one of the transistors; providing a plurality of gate signal lines connected to the gate electrode associated with any one of the transistors; and connecting a gate driver to the plurality of gate signal lines, the gate driver receiving first and second voltages and outputting at least one of the flirst and second voltages in such a manner. to sequentially drive the gate signal lines, the first voltage changing prior to driving successive gate signal lines, wherein the gate driver includes: a shift register for generating scanning signals to be applied respectively to 0 -M the gate lines, wherein the shift register is responsive to a gate scanning clocka level shifter making use of the first and second voltages to generate each voltage level of the scanning signals; and ID a voltage controller for changing the first voltage applied to the level shifter prior to disabling of the scanning signals.

19. The method of claim 18, wherein the voltage controller includes: a switch for cutting off the first voltage applied to the level shifter prior to disabling of the scanning signal; and a discharging path provided to the level shifter during period in which the scanning signal is cut off by means of the switch.

20. The method of claim 19, wherein the switch and the shift register respond to the gate scanning clock.

21. The method of claim 19, further comprising a timing controller for controlling the switch.

I 37 22. The method Of claim IS, wherein the voltage controller includes: an inpur terminal --or receiving the First voltage; a Erst resistor conneczed ber-tween the input e-minal and an 'input por-, ofthe level a tirst control switch and a second esistor connec-ted, in series berxeen the input port of the level shiilter ard, a _zround voltage line-, and a second control swirch connected in parallel to -,',,e 4,rsz resist0r, -, he secord control switch being dr-iiven alrer-nanvely with the Sirs-, cont-ol switch.

23. The method of any of claims t 8 to 22, wherein the shift register and the level shifter are 'tabricared to include in an integrated cir_uit chip- r -1 The method of any of clai rns IS to 72, whe, el n the shi t r. I i if egister, the voltage controller and the level shifter are fabricated to include in an integrated ciroult chip.

75. The met-hod of claim IS, wherein the voltage controller comprises a switch responsive to a gate output eriable signal and is connected between the First voltage and the level shifter.

2 6. The method of claim 25, wherein the gate output enable signal is inverse of the oate scanning clock- M -77. A liquid crystal display apparatus substantially as hereiribefore described with reference to and/or substantially as illustrated in any one or any combination of Figs. 5 to 26 of the accompany ing drawings.

23. A method of driving a liquid crystal display apparatus substantially as hereiribefore described with reference to and/or substantially as illustrated in any one or any combination of Figs. 5 to 26 of the accompanying drawings.

1 0 38 1,19. - A method ofinanufacturing a liquid crystal display apparatus substantially as her-".nbefore described with reterence to and/er substantially as illustrated in any one or any combination of Figs, 5 to 26 of the accompanying drawings.