JPH06110035A - Driving method for liquid crystal display device - Google Patents

Driving method for liquid crystal display device

Info

Publication number
JPH06110035A
JPH06110035A JP25840392A JP25840392A JPH06110035A JP H06110035 A JPH06110035 A JP H06110035A JP 25840392 A JP25840392 A JP 25840392A JP 25840392 A JP25840392 A JP 25840392A JP H06110035 A JPH06110035 A JP H06110035A
Authority
JP
Japan
Prior art keywords
waveform
transistor
display device
scanning signal
flicker
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25840392A
Other languages
Japanese (ja)
Inventor
Yuji Kawachi
裕二 河内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP25840392A priority Critical patent/JPH06110035A/en
Publication of JPH06110035A publication Critical patent/JPH06110035A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00Details of flat display driving waveforms
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0404Matrix technologies
    • G09G2300/0417Special arrangements specific to the use of low carrier mobility technology
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0247Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Abstract

PURPOSE:To obtain a fine image with high resolution by the active matrix display device by lowering the level of a flicker which causes the display quality to decrease while the irregularity of the flicker on a screen due to an increase in the capacity of gate lines for high density is a technical problem. CONSTITUTION:The rising waveform of a scanning line waveform is, for example, a ramp waveform, exponential function waveform, or staircase waveform. Thus, high frequency components are made small to reduce the potential drop of a pixel potential waveform outputted by a high-pass filter consisting of a transistor, a parasitic capacitance between scanning lines, and a resistance used by regarding the transistor as a variable resistance. Consequently, the flicker can be suppressed low and the image of high quality is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】液晶表示装置に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device.

【0002】[0002]

【従来の技術】従来のアクティブマトリックス液晶表示
体における走査線の信号は図6に示す矩形波をしてい
た。走査線に順次パルス幅分遅延させた走査信号を入力
することで走査線にある各画素のトランジスタのゲート
をオンさせ、各画素へ信号線より映像信号を書き込む動
作をしていた。NTSC方式のTV信号の場合では水平
走査期間分の63.5μsecのパルス幅で走査信号を
各ゲートラインに与え、その期間ずっと走査線に通ずる
トランジスタのゲートはオンした状態である。
2. Description of the Related Art A signal on a scanning line in a conventional active matrix liquid crystal display has a rectangular wave shown in FIG. By inputting a scanning signal which is sequentially delayed by a pulse width to the scanning line, the gate of the transistor of each pixel in the scanning line is turned on, and the video signal is written to each pixel from the signal line. In the case of the NTSC system TV signal, a scanning signal is applied to each gate line with a pulse width of 63.5 μsec for the horizontal scanning period, and the gate of the transistor connected to the scanning line is kept on during the period.

【0003】[0003]

【発明が解決しようとする課題】従来の走査線信号では
立ち下がり波形も矩形波の状態であるから、高周波成分
が高い信号である。一方図4に示す画素等価回路におい
てトランジスタ3のドレインとゲートで構成される寄生
容量6とトランジスタ3を可変抵抗と見なした場合の抵
抗で構成されるハイパスフィルター回路の出口が画素電
位である。つまり走査線の信号は高周波成分を持っため
減衰することなく、寄生容量6を介して画素電位に通じ
る。このため大きな電位降下ΔV(図5のΔV)が生
じ、フリッカーの原因となっている。又アクティブマト
リックス基板を用いて高密度化が可能ではあるが、この
画素電位の電位降下のため特に高密度の仕様ではゲート
ラインの容量が大きいため面内においてフリッカーのレ
ベルが異なる現象が生じる。
Since the falling waveform of the conventional scanning line signal is also a rectangular wave, the signal has a high high-frequency component. On the other hand, in the pixel equivalent circuit shown in FIG. 4, the exit of the high-pass filter circuit formed by the parasitic capacitance 6 formed by the drain and gate of the transistor 3 and the resistance when the transistor 3 is regarded as a variable resistance is the pixel potential. That is, since the signal of the scanning line has a high frequency component, the signal of the scanning line is not attenuated and communicates with the pixel potential through the parasitic capacitance 6. Therefore, a large potential drop ΔV (ΔV in FIG. 5) occurs, which causes flicker. Further, although it is possible to increase the density by using the active matrix substrate, due to the potential drop of the pixel potential, there occurs a phenomenon that the level of flicker is different in the plane because the capacitance of the gate line is large especially in the high density specifications.

【0004】これは共通電極電位を画面内のある位置に
おいてフリッカーの最小となる位置に合わせても、別の
位置ではフリッカーが生じるという現象が生じ、適正な
共通電極電位が存在しない状態になる。高密度化技術の
大きな課題点となっていた。
This causes a phenomenon in which even if the common electrode potential is adjusted to a position where flicker is minimized at a certain position in the screen, flicker occurs at another position, so that an appropriate common electrode potential does not exist. This has been a major issue in high-density technology.

【0005】[0005]

【課題を解決するための手段】マトリックス状にデータ
線と走査線が配置され、その交点部近くに少なくとも1
つ以上のスイッチングトランジスタを有し、該トランジ
スタのゲートが走査線に接続し又該トランジスタのソー
スがデータ線に接続され、さらに該トランジスタのドレ
インが透面画素電極に接続されたアクティブマトリック
ス基板を有する液晶表示装置において、その走査信号の
駆動方法での走査信号の立ち下がり波形がランプ波形又
は指数関数波形又は階段状波形であることを特徴とす
る。
Data lines and scan lines are arranged in a matrix, and at least one line is provided near the intersection.
An active matrix substrate having one or more switching transistors, a gate of the transistor connected to a scan line, a source of the transistor connected to a data line, and a drain of the transistor connected to a transparent pixel electrode In the liquid crystal display device, the falling waveform of the scanning signal in the driving method of the scanning signal is a ramp waveform, an exponential function waveform, or a stepped waveform.

【0006】[0006]

【作用】液晶表示体の中でアクティブマトリックス基板
を有する液晶表示体は画素数を増やして、同一画面サイ
ズに高密度に画素を配置させることができる。これによ
ってキメ細かな高解像度の鮮明な画面を実現できる。こ
うした高密度化技術の課題としてゲートラインに帰生す
る容量が増加し、画面内特に画面の左右で適正な共通電
極電位が異なる現象が生じる。これは面内で直流成分の
バラツキが生じることでフリッカーの分布が発生するこ
とを意味する。こうした画像はチラツキが多く大変見づ
らいものである。
The liquid crystal display having an active matrix substrate among the liquid crystal displays can increase the number of pixels and arrange pixels in the same screen size with high density. This makes it possible to realize a fine, high-resolution, clear screen. As a problem of such a high-density technique, the capacitance attributed to the gate line increases, and a phenomenon occurs in which an appropriate common electrode potential is different in the screen, especially on the left and right of the screen. This means that the flicker distribution occurs due to the variation of the DC component in the plane. These images are very flickering and very difficult to see.

【0007】このフリッカーの原因として考えられるも
のに画素の保持状態におけるゲートラインによる電位降
下が画面の左右で異なる事が挙げられる。図4はアクテ
ィブマトリックス基板の1画素の等価図であるがトラン
ジスタのドレイン部とゲートライン間の寄生容量6によ
って、図5に示す画素電位波形中の電位降下ΔVが生じ
ている。
One possible cause of this flicker is that the potential drop due to the gate line in the pixel holding state is different between the left and right sides of the screen. FIG. 4 is an equivalent diagram of one pixel on the active matrix substrate, but the potential drop ΔV in the pixel potential waveform shown in FIG. 5 occurs due to the parasitic capacitance 6 between the drain portion and the gate line of the transistor.

【0008】前述のフリッカーの面内分布を防止するた
めにはこの電位降下ΔVの効果を小さくすることが考え
られる。電位降下ΔVはゲートラインの電圧、つまり走
査信号と電圧と図4における画素容量と寄生容量の比に
よって決まる値である。画素容量と寄生容量はアクティ
ブマトリックス基板の仕様と構造で決ってくるので大き
な効果は期待できない。とすると走査信号の電圧によっ
て電位降下ΔVの値を小さくするわけであるが、走査信
号の電圧のハイレベルの電圧を低く押えることは画素へ
の書き込み能力を下げることになるので当然制約が生じ
る。ここで図4におけるトランジスタ3を一種の可変抵
抗と考えると画素電位は入力がゲートライン1の走査信
号で寄生容量6とトランジスタ(可変抵抗)3を介した
ハイパスフィルターの出口と考えられる。つまり走査信
号の高周波成分は電圧降下なく通す回路となっている。
In order to prevent the above-mentioned in-plane distribution of flicker, it is conceivable to reduce the effect of this potential drop ΔV. The potential drop ΔV is a value determined by the voltage of the gate line, that is, the scanning signal, the voltage, and the ratio of the pixel capacitance and the parasitic capacitance in FIG. Pixel capacitance and parasitic capacitance are determined by the specifications and structure of the active matrix substrate, so significant effects cannot be expected. Then, the value of the potential drop ΔV is reduced by the voltage of the scanning signal. However, holding down the high level voltage of the voltage of the scanning signal lowers the writing ability to the pixel, which naturally causes a limitation. If the transistor 3 in FIG. 4 is considered as a kind of variable resistor, the pixel potential is considered to be the scanning signal of the gate line 1 and the exit of the high pass filter via the parasitic capacitance 6 and the transistor (variable resistor) 3. In other words, it is a circuit that allows high-frequency components of the scanning signal to pass without voltage drop.

【0009】寄生容量6による電位降下ΔVを小さくす
るには走査信号の立ち下がり波形の高周波成分を無くす
る方法が考えられる。具体的には立ち下がり波形をラン
プ状又は指数関数波形にして緩やかな立ち下がりにする
ことである。又他には立ち下がり波形を階段状波形にす
ることでも同様の効果が期待できる。これらの形状の波
形にすることによって、走査信号による電位降下ΔVは
ハイパスフィルター回路の効果によって通常に比べ小さ
く押えることができる。ひいてはフリッカーのレベルを
押えることで面内の分布もめだたない程度に小さくする
ことが可能となる。
In order to reduce the potential drop ΔV due to the parasitic capacitance 6, a method of eliminating the high frequency component of the falling waveform of the scanning signal can be considered. Specifically, the falling waveform is formed into a ramp shape or an exponential function waveform so as to have a gentle falling. In addition, the same effect can be expected by forming the falling waveform into a stepwise waveform. With the waveforms of these shapes, the potential drop ΔV due to the scanning signal can be suppressed smaller than usual due to the effect of the high-pass filter circuit. By suppressing the flicker level, it is possible to reduce the in-plane distribution to a negligible extent.

【0010】[0010]

【実施例】本発明における走査信号電位波形を図1、図
2、図3に示す。図2は指数関数立ち下がり波形で、図
7に示す用に走査線入力部に抵抗8と容量7を付加する
ことで実現できる。液晶表示装置が外付けドライバー集
積回路を用いる場合は、ドライバーICの最終段に前述
の抵抗と容量を入れて実現できるし、又アクティブマト
リックス基板上で走査線入力部に抵抗と容量を入れても
可能である。これらの抵抗と容量の値を最適化して水平
帰線区間以内の時定数で立ち下げる様にする。但し立ち
上がりも同じ時定数で立ち上がるので、画素容量とデー
タ線への書き込みは充分速くできる能力は前提として必
要になる。立ち上がりの時定数の影響がない範囲内で走
査線の立ち下がり波形を指数関数波形にすることで、走
査線波形の高周波成分を無くし画素電位波形の電位降下
を緩和することが可能となる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Scanning signal potential waveforms according to the present invention are shown in FIGS. FIG. 2 shows a falling waveform of an exponential function, which can be realized by adding a resistor 8 and a capacitor 7 to the scanning line input section as shown in FIG. When the liquid crystal display device uses an external driver integrated circuit, it can be realized by inserting the above-mentioned resistor and capacitor in the final stage of the driver IC, or by inserting the resistor and capacitor in the scanning line input section on the active matrix substrate. It is possible. The values of these resistances and capacitances are optimized so that they fall with a time constant within the horizontal blanking interval. However, since the rising time also rises with the same time constant, the pixel capacity and the ability to write to the data line sufficiently fast are necessary. By making the falling waveform of the scanning line into an exponential function waveform within a range where there is no influence of the rising time constant, it is possible to eliminate the high frequency component of the scanning line waveform and mitigate the potential drop of the pixel potential waveform.

【0011】さらに指数関数波形を実現する他の方法と
して図8に示す様にバッファーとしてのインバーターを
入れてそのトランジスタサイズを最適化する方法があ
る。ドライバー回路が内蔵されたアクティブマトリック
ス基板では最終段バッファー回路のインバーターのサイ
ズ及び電流特性を最適化することで同様の効果が得られ
る。
As another method for realizing the exponential function waveform, there is a method of inserting an inverter as a buffer to optimize the transistor size as shown in FIG. The same effect can be obtained by optimizing the size and current characteristics of the inverter of the final stage buffer circuit in the active matrix substrate in which the driver circuit is incorporated.

【0012】又前述の抵抗の材料としてはポリシリコン
TFTでは、ゲート電極材料のドープされたポリシリコ
ンが考えられ、アモルファスシリコンTFTではN+
モルファスシリコン等を利用することが考えられる。
Further, as the material of the above-mentioned resistor, in the polysilicon TFT, doped polysilicon of the gate electrode material is considered, and in the amorphous silicon TFT, N + amorphous silicon or the like may be used.

【0013】図1に示すのが本発明の走査信号の立ち下
がり波形の中のランプ波形で、図9に示すオペアンプを
利用した回路を走査線の入力前に入れることで実現が可
能となる。ランプ波にすることによって図4のハイパス
フイルターにおける可変抵抗とみなしたトランジスタ3
を通って逃げる電荷の量が、矩形波に比べ多くなり、振
幅が小さくなる。つまり画素の電位降下の量は小さくな
り、フリッカーも押えられることになる。
FIG. 1 shows a ramp waveform in the falling waveform of the scanning signal of the present invention, which can be realized by inserting the circuit using the operational amplifier shown in FIG. 9 before inputting the scanning line. Transistor 3 regarded as a variable resistance in the high-pass filter of FIG. 4 by making a ramp wave
The amount of electric charge that escapes through becomes larger than that of the rectangular wave, and the amplitude becomes smaller. That is, the amount of potential drop in the pixel is reduced, and flicker is suppressed.

【0014】又ランプ波立ち下がりの時間は水平帰線区
間内である必要があり、NTSC方式のビデオ信号であ
れば10.9μ秒以内ということになる。
Further, it is necessary that the fall time of the ramp wave is within the horizontal blanking interval, which is within 10.9 μs for an NTSC video signal.

【0015】さらに図3に示すのが本発明の走査信号の
立ち下がり波形の中の階段状波形である。図10に示す
ブロック図がこの実施例の回路であり、前述の立ち下が
りランプ波形発生回路の後にアナログスイッチ12を設
け、そのゲートパルスとして階段波発生タイミングパル
スを入力する。図11にそれらの波形を示す。13がゲ
ート立ち下がりランプ波電圧波形で、14が階段波発生
用タイミングパルスの電圧波形である。この時のアナロ
グスイッチ12の出力である走査信号波形を図12に示
す。15が本発明の階段波形で、タイミングパルス14
のデューティー比を最適化することで図3に示す波形に
近付けることが可能となる。他の方法としては図13の
ブロック回路図に示すサンプルホールド回路を利用し階
段波を作成する方法がある。サンプリングスイッチSを
閉じるとランプ波形回路からの出力ランプ波形の振幅値
に等しい電圧でコンデンサCに充電し、次にサンプリン
グスイッチSを開くとコンデンサの充電電圧が保持され
出力される。サンプリングスイッチSのサンプリング時
間のタイミングを最適化し所定の階段波を発生させるこ
とが可能となる。
Further, FIG. 3 shows a stepwise waveform in the falling waveform of the scanning signal of the present invention. The block diagram shown in FIG. 10 is the circuit of this embodiment. An analog switch 12 is provided after the above-described falling ramp waveform generation circuit, and a staircase wave generation timing pulse is input as its gate pulse. FIG. 11 shows those waveforms. Reference numeral 13 is a gate falling ramp wave voltage waveform, and 14 is a voltage waveform of a staircase generation timing pulse. The waveform of the scanning signal output from the analog switch 12 at this time is shown in FIG. 15 is a staircase waveform of the present invention, which is a timing pulse 14
It is possible to approximate the waveform shown in FIG. 3 by optimizing the duty ratio of. As another method, there is a method of creating a staircase wave using the sample hold circuit shown in the block circuit diagram of FIG. When the sampling switch S is closed, the capacitor C is charged with a voltage equal to the amplitude value of the output ramp waveform from the ramp waveform circuit, and when the sampling switch S is opened next, the capacitor charging voltage is held and output. It is possible to optimize the timing of the sampling time of the sampling switch S and generate a predetermined staircase wave.

【0016】[0016]

【発明の効果】本発明の液晶表示装置の駆動方法におい
て走査信号を図1に示すランプ波、又は図2に示す指数
関数波、又は図3に示す階段波の立ち下がり波形にする
ことによって、走査信号の高周波成分を小さくすること
ができる。図4に示すハイパスフィルター出口が画素電
位であることから、走査線波形による画素電位降下を小
さくすることができ、フリッカーを低く押えることが可
能となる。さらにアクティブ液晶表示装置においては画
素の高密度化におけるフリッカー画面内ムラを回避する
ことが可能となり、キメ細かな高解像度の画像を実現す
ることが可能となる。
According to the driving method of the liquid crystal display device of the present invention, the scanning signal is made into the ramp wave shown in FIG. 1, the exponential function wave shown in FIG. 2, or the falling waveform of the staircase wave shown in FIG. The high frequency component of the scanning signal can be reduced. Since the exit of the high-pass filter shown in FIG. 4 is the pixel potential, the pixel potential drop due to the scanning line waveform can be reduced, and the flicker can be suppressed low. Further, in the active liquid crystal display device, it is possible to avoid unevenness in the flicker screen due to high pixel density, and it is possible to realize a fine high-resolution image.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の走査信号ランプ波立ち下がり波形
図。
FIG. 1 is a falling waveform diagram of a scanning signal ramp wave according to the present invention.

【図2】 本発明の走査信号指数関数波立ち下がり波形
図。
FIG. 2 is a falling waveform diagram of a scanning signal exponential wave according to the present invention.

【図3】 本発明の走査信号階段波立ち下がり波形図。FIG. 3 is a waveform diagram of a falling edge of a scanning signal staircase according to the present invention.

【図4】 本発明の1画素等価回路路図。FIG. 4 is a one-pixel equivalent circuit diagram of the present invention.

【図5】 従来の技術の画素電位波形図。FIG. 5 is a pixel potential waveform diagram of a conventional technique.

【図6】 従来の技術の走査信号電位波形図。FIG. 6 is a scanning signal potential waveform diagram of a conventional technique.

【図7】 本発明の走査信号指数関数波立ち下がり波発
生回路ブロック図。
FIG. 7 is a block diagram of a scanning signal exponential wave falling wave generation circuit of the present invention.

【図8】 本発明の走査信号指数関数波立ち下がり波発
生回路ブロック図。
FIG. 8 is a block diagram of a scanning signal exponential wave falling wave generation circuit of the present invention.

【図9】 本発明の走査信号ランプ波立ち下がり波形発
生回路ブロック図。
FIG. 9 is a block diagram of a scanning signal ramp wave falling waveform generation circuit according to the present invention.

【図10】 本発明の走査信号階段波立ち下がり波形発
生回路ブロック図。
FIG. 10 is a block diagram of a scanning signal staircase falling waveform generation circuit according to the present invention.

【図11】 本発明の走査信号階段波立ち下がり波形発
生回路ブロックの電圧波形図。
FIG. 11 is a voltage waveform diagram of the scanning signal staircase falling waveform generation circuit block of the present invention.

【図12】 本発明の走査信号階段波立ち下がり波形
図。
FIG. 12 is a waveform diagram of a falling edge of a scanning signal staircase according to the present invention.

【図13】 本発明の走査信号階段波発生回路ブロック
図。
FIG. 13 is a block diagram of a scanning signal staircase generation circuit of the present invention.

【符号の説明】[Explanation of symbols]

1 走査線 2 データ線 3 トランジスタ 4 画素容量 5 共通電極電位 6 トランジスタと走査線間の寄生容量 7 指数関数立ち下がり波発生容量 8 指数関数立ち下がり波発生抵抗 9 指数関数立ち下がり波発生インバーター 10 オペアンプ 11 インバーター 12 アナログスイッチ 13 ランプ立ち下がり波形 14 階段波発生用タイミングパルス 15 階段状立ち下がり走査信号波形 16 サンプルホールド回路中のオペアンプ 17 サンプリングスイッチ 1 Scan Line 2 Data Line 3 Transistor 4 Pixel Capacitance 5 Common Electrode Potential 6 Parasitic Capacitance Between Transistor and Scan Line 7 Exponential Function Falling Wave Generation Capacitance 8 Exponential Function Falling Wave Generation Resistance 9 Exponential Function Falling Wave Generation Inverter 10 Operational Amplifier 11 Inverter 12 Analog Switch 13 Ramp Falling Waveform 14 Staircase Wave Generation Timing Pulse 15 Stepwise Falling Scan Signal Waveform 16 Operational Amplifier in Sample Hold Circuit 17 Sampling Switch

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 マトリックス状にデータ線と走査線が配
置され、その交点部近くに少なくとも1つ以上のスイッ
チングトランジスタを有し、該トランジスタのゲートが
走査線に接続し、又該トランジスタのソースがデータ線
に接続され、さらに該トランジスタのドレインが透明画
素電極に接続されたアクティブマトリックス基板を有す
る液晶表示装置において、走査信号の電圧波形における
パルスの立ち下がり波形がランプ波形となっていること
を特徴とする液晶表示装置の駆動方法。
1. A data line and a scan line are arranged in a matrix, and at least one switching transistor is provided near an intersection of the data line and the scan line, the gate of the transistor is connected to the scan line, and the source of the transistor is In a liquid crystal display device having an active matrix substrate connected to a data line and having a drain of the transistor connected to a transparent pixel electrode, a falling waveform of a pulse in a voltage waveform of a scanning signal is a ramp waveform. And a method for driving a liquid crystal display device.
【請求項2】 請求項1記載の液晶表示装置において走
査信号の電圧波形におけるパルスの立ち下がり波形が指
数関数波形となっていることを特徴とする液晶表示装置
の駆動方法。
2. The method of driving a liquid crystal display device according to claim 1, wherein the falling waveform of the pulse in the voltage waveform of the scanning signal is an exponential function waveform.
【請求項3】 請求項1記載の液晶表示装置において走
査信号の電圧波形におけるパルスの立ち下がり波形が階
段状波形となっていることを特徴とする液晶表示装置の
駆動方法。
3. A method of driving a liquid crystal display device according to claim 1, wherein the falling waveform of the pulse in the voltage waveform of the scanning signal is a stepwise waveform.
JP25840392A 1992-09-28 1992-09-28 Driving method for liquid crystal display device Pending JPH06110035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25840392A JPH06110035A (en) 1992-09-28 1992-09-28 Driving method for liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25840392A JPH06110035A (en) 1992-09-28 1992-09-28 Driving method for liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH06110035A true JPH06110035A (en) 1994-04-22

Family

ID=17319751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25840392A Pending JPH06110035A (en) 1992-09-28 1992-09-28 Driving method for liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH06110035A (en)

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