JP2000137247A - Active matrix liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to remove flicker and after-image and to simplify circuit constitution by providing a gate driver or the like capable of outputting one of a first voltage and a second voltage and allowing the first voltage to change before continued gate signal lines are activated. SOLUTION: The device has a data driver 32 for driving signal lines SL1-LSm provided on a liquid crystal panel 30 and a gate driver 34 for driving gate lines GL1-GLn provided on the liquid crystal panel 32. Further, relating to this active matrix liquid crystal display device, the falling part of scanning signal is changed in a form selected from linear, exponential and step functions by supplying a high gate voltage to a level shift of the gate driver 34 in the alternating current form. Thereby, a field through voltage is sufficiently suppressed and then formation of flicker and after-image can be avoided and, at the same time, the circuit constitution is extremely simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display device, and more particularly to an active matrix liquid crystal display device having means for supplying a gate pulse to a transistor connected to a pixel formed of liquid crystal.

[0002]

2. Description of the Related Art A conventional active matrix liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device has a signal line (SL) on a liquid crystal panel 10 as shown in FIG.
1 to SLm), and a data driver (12)
Gate lines (GL1 to GL) on the liquid crystal panel (10)
n) for driving n). Pixels 11 connected to the signal lines SL and the gate lines GL are arranged in the liquid crystal panel 10 in an active matrix form. Each of the pixels (11) has a data voltage signal (D) from the signal line (SL).
VS), the liquid crystal cell (Cl
c) and a thin film transistor (hereinafter referred to as “TFT”) for switching a data voltage signal (DVS) supplied to the liquid crystal cell (Clc) from the signal line (SL) in response to a scanning signal (SCS) from the gate line (GL). )
(CMN). The data driver 12 supplies the data voltage signal (DVS) to all the signal lines (SL1 to SLm) by sequentially driving the gate lines (GL1 to GLn). On the other hand, the gate driver (14) sequentially supplies the scanning signal (SCS) to the gate lines (GL1 to GLn), so that the gate lines (GL1 to GLn) are sequentially driven for each horizontal synchronization period. For this purpose, the gate start pulse (GSP) from the control line (CL) and the gate scanning clock (GS) from the gate scanning clock (GSL) from the gate clock line (GCL) are used.
L), and a level shift (18) connected between the shift register (16) and the gate lines (GL1 to GLn). The shift register (16) outputs the gate start pulse (GSP) from the control line (CL) to any one of the n output terminals (QT1 to QTn), and outputs a gate scanning clock. The gate start pulse (GSP) is sequentially moved from the first output terminal (QT1) to the n-th output terminal (QTn) in response to (GSC). The level shift (18) shifts the voltage level of the output signal of the shift register (16) to generate n scanning signals (SCS). For this purpose, the level shift (18) uses the shift register (1).
6) connected between the n output terminals (QT1 to QTn) and the n gate lines (GL), respectively, and in the form of DC from the first and second voltage lines (FVL, SVL). It is composed of n inverters (19) receiving supply of low potential and high potential voltages (Vgl, Vgh).
The inverter (19) selectively supplies one of the low potential and the high potential voltage (Vgl, Vgh) to the gate line (GL) according to the logic state from the output terminal (QT) of the shift register (16). I do. Thus, only one of the n scanning signals (SCS) has the high potential gate voltage (Vgh). When the scanning signal (SCS) having the high potential gate voltage (Vgh) is supplied from the gate line (GL), the TFT (CM)
N) is turned on (Turn-On), and the liquid crystal cell (Clc) applies the data voltage signal (D) during the period when the TFT (CMN) is started.
VS). Thus, the voltage charged in the liquid crystal cell (Clc) decreases when the TFT (CMN) is turned on (Turn-On), so that it becomes lower than the voltage of the data voltage signal (DVS). A feedthrough voltage (ΔVp) corresponding to a potential difference between the voltage charged in the liquid crystal cell and the data voltage signal (DVS) is generated. The feedthrough voltage (ΔVp) is generated by a parasitic capacitance existing between the gate terminal of the TFT (CMN) and the liquid crystal cell (Clc), and periodically changes the light transmission amount of the liquid crystal cell (Clc). As a result, flicker and an afterimage occur in pixels displayed on the liquid crystal panel.

[0003] Such a feed-through voltage (ΔVp)
As a method for suppressing this, the storage capacitor (Cst) is connected in parallel to the liquid crystal cell (Clc) as shown in FIG. The auxiliary capacitance (Cst) suppresses the feedthrough voltage (ΔVp) as shown in Equation 1 by supplementing the liquid crystal cell voltage that decreases when the TFT (CMN) is turned off.

(Equation 1) In Equation 1, Von is the voltage on the gate line (GL) when the TFT (CMN) is activated, and Voff is the TFT (CMN).
(CMN) is the voltage on the gate line (GL) at the time of turning off, and Cgs is the capacitance of the parasitic capacitance existing between the gate terminal of the TFT (CMN) and the liquid crystal cell. As shown in Equation 1, the feedthrough voltage (ΔVp) is equal to the TFT (CM
N) Gate line at start-up and turn-off (GL)
It increases with the above voltage difference. In order to sufficiently suppress such a feedthrough voltage (ΔVp), the capacity of the auxiliary capacitor (Cst) must be increased.
Since the aperture ratio (Aperture Ratio) of the display area becomes small, sufficient display contrast cannot be obtained. As a result, the feedthrough voltage (ΔVp) cannot be sufficiently suppressed depending on the auxiliary capacitance (Cst).

As a method for suppressing the feedthrough voltage (ΔVp), there has been proposed a scanning signal control type liquid crystal display device in which the falling portion of the scanning signal (SCS) is made gentle. In the scanning signal control type liquid crystal display device, the falling portion of the scanning signal (SCS) changes in the form of a linear function as shown in FIG. 2A, an exponential function as shown in FIG. 2B, or a step function as shown in FIG. 2C. . Such a scanning signal control type liquid crystal display device is disclosed in JP-A-6-110035 and JP-A-9-258.
174 and U.S. Pat. No. 5,587,722. However, these scanning signal control type liquid crystal display devices require a gate driver circuit modification or a new waveform modification circuit located between the gate driver and each gate line on the liquid crystal panel. Also,
In the gate driver disclosed in U.S. Pat. No. 5,587,722, a circuit having a function of making a falling portion of a scanning signal stepwise is formed in one gate driver chip, so that the circuit is formed. It becomes complicated and consumes much power.

In fact, a scanning signal control type liquid crystal display device disclosed in Japanese Patent Laid-Open No. 6-110035 is shown in FIG.
Has an integrator (22) connected between the scanning driver cell (20) and the gate line (GL). The integrator (22) includes a resistor (R1) connected between the scanning driver cell (20) and the gate line (GL), and a capacitor (R1) connected between the gate line (GL) and the ground voltage line (GVL). C1). The integrator (22) configured as described above integrates the scanning signal supplied from the gate driver cell (20) to the gate line (GL) side so that the falling portion of the scanning signal (SCS) exponentially functions. Change. The TFT (CMN) included in the pixel (11) is activated until the voltage of the scanning signal (SCS) from the gate line (GL) drops below its own critical voltage. At this time, the charge charged in the liquid crystal cell (Clc) is pumped to the gate line (GL) side via the parasitic capacitance (Cgs), so that the charge amount is extremely small. As a result,
The feedthrough voltage (ΔVp) is sufficiently suppressed.

[0006]

In the above-described scanning signal control type liquid crystal display device, the flicker and the afterimage are significantly reduced by sufficiently suppressing the feedthrough voltage (ΔVp). Since a waveform transformation circuit such as an integrator must be added, the circuit configuration becomes very complicated. At the same time, the waveform changing circuit gradually changes the scanning signal up to the rising portion, so that the charging start time of the liquid crystal cell is delayed.

On the other hand, US Pat. No. 5,587,722
No. 3 discloses a shift register (3) for selectively inputting power supply voltages (VVDD and VVDD.R1 / (R1 + R2)) as shown in FIG. The shift register (3) is provided with a power supply voltage (VVDD and VVDD ・ R1 /
A staircase pulse is generated in response to (R1 + R2)).
However, the shift register (3) must be driven at a high voltage because the power supply voltage is the same as the high-level gate voltage supplied to the gate lines on the liquid crystal panel. That is, the inverters (5, 6,
9) operates with a drive voltage of about 25 V when the maximum voltage for starting the TFT is 2.5 V. Accordingly, the active matrix liquid crystal display device disclosed in US Pat. No. 5,587,722 consumes a large amount of power.

Accordingly, an object of the present invention is to provide an active matrix liquid crystal display device which is adapted to eliminate flicker and afterimages and to simplify the circuit configuration, and a driving method thereof.

[0009]

In order to achieve the above object, an active matrix liquid crystal display device according to the present invention comprises a gate electrode, a second electrode connected to a first electrode and a pixel electrode.
A plurality of pixels arranged in a matrix with each including a switch transistor having an electrode;
A plurality of data signal lines respectively connected to a first electrode corresponding to one of the plurality of transistors; a plurality of gate signal lines connected to a gate electrode corresponding to one of the plurality of transistors; A gate connected to the plurality of gate signal lines, receiving first and second voltages, and outputting one of the first and second voltages so that the gate signal lines are sequentially driven; And a driver. The first voltage changes before the continuous gate signal line is activated.

A method of driving an active matrix liquid crystal display according to the present invention includes a second method which periodically changes with a first voltage.
Inputting a voltage; supplying a second voltage to the gate line via a switch element; and supplying the first voltage to the gate line via a switch.
The switch element is controlled by the shift register, and the minimum value of the second voltage is set higher than the maximum value of the first voltage.

[0011]

With the above arrangement, in the active matrix liquid crystal display device according to the present invention, the falling portion of the scanning signal has a linear, exponential or step function when the high potential gate voltage is supplied in an alternating current mode to the level shift of the gate driver. It changes in any one of the forms. As a result, in the active matrix liquid crystal display device according to the present invention, the feedthrough voltage (ΔVp) is sufficiently suppressed, and flicker and afterimages do not occur. In addition, in the active matrix liquid crystal display device according to the present invention, the falling portion of the high potential gate voltage changes more gently than the rising portion, so that the falling portion of the scanning signal supplied to the gate line changes more gently than the rising portion. . Accordingly, in the active matrix liquid crystal display device according to the present invention, the flicker and the afterimage are not generated, and the response speed is increased.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.
Referring to FIG. 5, a data driver (3) for driving signal lines (SL1 to SLm) on the liquid crystal panel (30).
2) and a gate line (GL1) on the liquid crystal panel (30).
To GLn) (34)
An active matrix liquid crystal display according to a first embodiment of the present invention, comprising: In the liquid crystal panel (30), the signal line (SL) and the gate line (G
The pixels (31) connected to L) are arranged in an active matrix form. Each of the pixels (31) responds to a liquid crystal cell (Clc) for adjusting the amount of transmitted light in response to a data voltage signal (DVS) from a signal line (SL) and a scanning signal (SCS) from a gate line (GL). TFT (C) for switching the data voltage signal (DVS) supplied from the signal line (SL) to the liquid crystal cell (CLc)
MN). In each of the pixels (31), an auxiliary capacitance (Cst) is connected in parallel to the liquid crystal cell (Clc). This auxiliary capacitance (Cst) is a liquid crystal cell (Clc).
Buffer the charged voltage. Data driver (32)
Supplies a data voltage signal (DVS) to all of the gate lines (GL1 to GLn). Gate driver (34)
Supplies the scanning signal (SCS) to the gate line (GL1).
To GLn) to the gate line (GL)
1 to GLn) are sequentially enabled for each horizontal synchronization period. For this purpose, the gate driver (34) responds to the gate start pulse (GSP) from the control line (CL) and the gate scanning clock (GSC) from the gate clock line (GCL).
6), shift register (36) and gate line (GL)
Level shift (38) connected between 1 to GLn)
It consists of. The shift register (36) outputs the gate start pulse (GSP) from the control line (CL) to any one of the n output terminals (QT1 to QTn). A gate start pulse (GSP) is supplied from the first output terminal (QT1) to the n-th gate in response to the gate scanning clock (GSC).
It is sequentially moved to the output terminal (QTn) side. Also, the shift register (36) has a voltage of 5V corresponding to the logic voltage level.
It operates with an integrated circuit drive voltage having N output terminals (QT1 to QTn) of the level shift register (36)
And n gate lines (GL), and the first and second voltage lines (FVL, SVV).
L) and low and high potential gate voltages (Vgl, Vg
h control switches (39) for switching h)
And The control switch 39 selectively selects one of the low-potential and high-potential gate voltages (Vgl, Vgh) according to the logic state from the output terminal (QT) of the shift register 36. ). Thereby, n scanning signals (SCS)
Has a high potential gate voltage (Vgh). The TFT (CMN) on the gate line (GL) to which the high potential gate voltage (Vgh) is applied starts (Tu
rn-On), and the liquid crystal cell (Clc) applies the data voltage signal (D) during the period when the TFT (CMN) is activated.
VS). Each of the control switches (39) may be opposed to a burper that uses low-potential and high-potential gate voltages (Vgl, Vgh) as operating voltages.

The liquid crystal display according to the first embodiment of the present invention includes a low-potential gate voltage generator (40) connected to the first voltage line (FVL) and a high-potential gate voltage generator (42). Provide additionally. The low-potential gate voltage generator (40) generates a low-potential gate voltage (Vgl) whose voltage level is kept constant, and supplies the low-potential gate voltage (Vgl) to n control switches (39) connected to the first voltage line (FVL). Supply.
The low potential gate voltage (Vgl) generated by the low potential gate voltage generator (40) may have the form of an AC signal such as a pulse signal having a constant period. The high-potential gate voltage generator (42) is a high-potential gate voltage (Vgh) that changes in a constant form every cycle of the horizontal synchronizing signal like an AC signal.
Occurs. This high-potential gate voltage (Vgh) has a falling portion that gradually changes gradually. The falling portion of the high potential gate voltage (Vgh) changes in the form of a linear function, changes in the form of an exponential function, or changes in the form of a step function. Such a high potential gate voltage (Vg
h) to generate a high-potential gate voltage generator (4
2) a high-potential voltage generator (44) for generating a high-potential voltage (VDD); and a voltage regulator (46) connected between the high-potential voltage generator (44) and the second voltage line (SVL).
And a timing controller (48) for controlling the level adjustment timing of the voltage regulator (46). The high-potential voltage generator (44) supplies a high-potential voltage (VDD) in a DC form to the voltage regulator (46) to maintain a constant voltage level in a stable manner. The voltage regulator (46) periodically transmits the high potential voltage (VDD) to the n control switches (39) connected to the second voltage line (SVL), and simultaneously outputs the high potential voltage (VDD). ) Is cut off, the voltage supplied to the second voltage line (SVL) is reduced in any one of the above-mentioned functional forms. In order to gradually change the falling portion of the voltage signal on the second voltage line (SVL), the voltage regulator (46) includes a parasitic resistance (Rp) and a parasitic resistance (Rp) existing on the gate line (GL) of the liquid crystal panel (30). Parasitic capacitance (Cp) can also be used. The timing controller (48) has a synchronous control line (SC).
L) in response to the horizontal synchronizing signal (HS) from the data clock line (DCL) and the data clock (DCLK) from the data clock line (DCL). For this purpose, the timing controller (4)
8) A counter (not shown) for countering the data clock (DCLK) in addition to being initialized by the horizontal synchronizing signal (HS) and a voltage regulator (46) by logically combining the output signal of this counter. May be configured by a logical combination unit (not shown) for controlling

As described above, since the high potential gate voltage (Vgh) on the second voltage line (SVL) has a falling portion that is gradually reduced in conjunction with the change in the AC form, the liquid crystal panel (30) ), The falling portion of the scanning signal (SCS) supplied to the gate line (GL) gradually changes. TFT (CM) included in the pixel (31)
N) is activated until the voltage of the scanning signal (SCS) from the gate line (GL) falls below its own critical voltage. At this time, a sufficient charge is supplied to the liquid crystal cell (Clc) by the data voltage signal (DVS) supplied from the signal line (SL) and supplied from the signal line (SL) through the TFT (CMN) or supplied to the gate line (GL). Cell (C
lc). Thereby, the liquid crystal cell (Cl
The voltage charged in c) does not decrease. The voltage of the scanning signal (SCS) on the gate line (GL) is TF
When the voltage drops below the threshold voltage of T (CMN), the amount of voltage fluctuation from the gate line (GL) to the gate line (GL) is the critical voltage of the maximum TFT (CMN). The amount of charge flowing to the ()) side is extremely small. As a result, the feedthrough voltage (ΔVp) is sufficiently suppressed.

FIG. 6 schematically illustrates an active matrix liquid crystal display according to a second embodiment of the present invention. FIG.
In the active matrix liquid crystal display device, the voltage regulator (46) is connected to the gate line (GL) of the liquid crystal panel (30).
Of the high-potential gate voltage (Vgh) and the falling portion of the scanning signal (SCS) by using the parasitic resistance (Rp) and the parasitic capacitance (Cp).
gh) and the falling portion of the scanning signal (SCS) are changed in an exponential form. In the liquid crystal display device of FIG. 6, a gate line (G
L) is included. The liquid crystal panel (30) includes a pixel (31) located at a connection with the signal line (SL) and the gate line (GL). The pixel (31) responds to the data voltage signal (DVS) from the signal line (SL) to adjust the amount of transmitted light in response to the data voltage signal (DVS), and responds to the scanning signal (SCS) from the gate line (GL). The data voltage signal (DV) supplied to the liquid crystal cell (Clc) from the signal line (SL)
S) is configured by a TFT (CMN) for switching. In the pixel (31), the storage capacitor (Cst) is connected in parallel to the liquid crystal cell (Clc). Gate driver (3
4) a shift register cell (36A) responding to a gate start pulse (GSP) from the control line (CL) and a gate scanning clock (GSC) from the gate clock line (GCL);
6A) and a control switch (39) connected between the gate line (GL). The shift register cell 36A outputs a gate start pulse (GSP) to the output terminal (QT) at the rising edge of the gate scanning clock (GSC) as shown in FIG. The control switch (39) is a shift register cell (36A)
One of the low-potential and high-potential gate voltages (Vgl, Vgh) is selectively supplied to the gate line (GL) according to the logic state of the output signal. Accordingly, the scanning signal (SC) having a low potential gate voltage or a high potential gate voltage (Vgh) is applied to the gate line (GL).
S) appears. More specifically, when the output signal of the shift register cell (36A) has a high logic, the control switch (39) operates at a high potential gate voltage (Vg).
h) is supplied to the gate line (GL), while the low potential gate voltage (Vgl) is supplied to the gate line (GL) when the output signal of the shift register cell (36A) has a low logic. To do. “SCSn” shown in FIG. 7 represents the waveform of the scanning signal supplied to the next gate line.

An active matrix liquid crystal display according to a second embodiment of the present invention includes a first voltage line (FV).
L) a low potential gate voltage generator (40) connected to
A high potential gate voltage generator (42) is additionally provided.
The low-potential gate voltage generator (40) includes a low-potential gate voltage (V) whose voltage level is maintained constant or periodically alternated.
gl) is supplied to n control switches (39) connected to the first voltage line (FVL). The high-potential gate voltage generator (42) generates a high-potential gate voltage (Vgh) that changes as shown in FIG. The falling portion of the high-potential gate voltage (Vgh) gradually decreases in the form of an exponential function. Thus, the high potential gate voltage (V
gh) to generate a high-potential gate voltage generator (4
2) a high-potential voltage generator (44) for generating a high-potential voltage (VDD), and a voltage regulator (46) connected between the high-potential voltage generator (44) and the second voltage line (SVL).
It consists of. The high-potential voltage generator (44) is a DC-type high-potential voltage (VD) for stably maintaining a constant voltage level.
D) to the voltage regulator (46). Voltage regulator (4
6) Alternately connecting the second voltage line (SVL) to the high potential voltage generator (44) and the base voltage line (GVL) so that the second voltage line (SVL) is as shown in FIG. A high potential gate voltage (Vgh) is generated. To this end, the voltage regulator (46) is a two-contact control switch (50) responsive to a gate scanning clock (GSC).
Is provided. The two-contact control switch (50) is the first switch in the high logic section of the gate scanning clock (GSC).
The high potential voltage (VDD) appears on the second voltage line (SVL) and the gate line (GL) by connecting the voltage line (SVL) to the high potential voltage generator (44). When the gate scanning clock (GSC) transitions from a high logic to a low logic, the two-contact control switch (50) connects the second voltage line (SVL) to the base voltage line (GVL), thereby connecting the second voltage line (GVL). SV
L) and the voltage on the gate line (GL) drops exponentially from the high potential voltage level (VDD). At this time,
The voltage on the second voltage line (SVL) and the gate line (GL) is discharged toward the base voltage line (GVL) by the time constant of the parasitic resistance (Rp) and the parasitic capacitance (Cp), so that the high potential gate voltage ( Vgh) and the falling portion of the scanning signal (SCS) gradually change in the form of an exponential function as shown in FIG. Thereby, the pixel (31)
Of the TFT (CMN) is kept on until the voltage of the scanning signal (SCS) from the gate line (GL) falls below the critical voltage. At this time, the charges charged in the liquid crystal cell (Clc) are transferred to the gate line (G
L) flows from the signal line (SL) to the TFT (C
MN), the liquid crystal cell (Clc) is charged with sufficient charge by the data voltage signal (DVS). As a result, the voltage charged in the liquid crystal cell (Clc) does not decrease. The scanning signal (S) on the gate line (GL)
CS) falls below the critical voltage of the TFT (CMN), the amount of voltage fluctuation at the gate line (GL) is T
Since it is the critical voltage of FT (CMN), the liquid crystal cell (Cl
The amount of charge flowing from c) to the gate line (GL) side is extremely small. As a result, the feedthrough voltage (ΔV
p) is sufficiently suppressed. Further, flicker and an afterimage do not occur at the image point displayed by the pixel (31).

FIG. 8 schematically illustrates an active matrix liquid crystal display according to a third embodiment of the present invention. FIG.
In the active matrix liquid crystal display device, a voltage regulator (46) includes a resistor (R1) and a capacitance (C1) between a switch (50) for controlling two contacts and a ground voltage line (GVL).
The liquid crystal display device of FIG. 6 has the same circuit configuration except that the liquid crystal display device of FIG. The resistance R1 and the capacitance C1 increase a time constant when the voltage on the second voltage line SVL and the gate line GL is discharged toward the base voltage line GVL. Accordingly, the falling portion of the high-potential gate voltage (Vgh) on the second voltage line (SVL) becomes more gentle than the rising portion as shown in FIG. At the same time, the falling part of the scanning signal (SCS) on the gate line (GL) also changes more gradually than the rising part as shown in FIG. Only one of the resistor (R1) and the capacitor (C1) may be used as necessary. Only one of the resistor (R1) and the capacitor (C1) may be used as necessary. By adjusting the falling portion of the high-potential gate voltage (Vgh) and the scanning signal (SCS) more gently than the rising portion, the liquid crystal display device can sufficiently suppress the feedthrough voltage (ΔVp). At the same time, the response speed increases.

FIG. 10 schematically illustrates an active matrix liquid crystal display according to a fourth embodiment. The active matrix liquid crystal display device shown in FIG.
6) is a switch (52) connected between the high-potential voltage generator (44) and the second voltage line (SVL) instead of the switch (50) for controlling two contacts, and a switch (52) for controlling one contact.
Except for having a TFT (MN) connected between the voltage line (SVL) and the base voltage line (GVL), it has the same circuit configuration as the liquid crystal display of FIG. 1
The switch (52) for contact control and the TFT (MN) are activated complementarily by the logic state of the gate scanning clock (GSC). To explain this in detail, 1
The contact control switch (52) is activated while the gate scanning clock (GSC) maintains the high logic,
On the other hand, the TFT (MN) is activated while the gate scanning clock (GSC) maintains high logic. The TFT (MN) provides a discharge path to the second voltage line (SVL) and the gate line (GL) according to the gate scanning clock (GSC), so that the high potential gate voltage (Vgh) and the falling portion of the scanning signal (GL) are provided. Changes exponentially. In addition, TFT (M
N) increases the time constant when the voltage on the second voltage line (SVL) and the gate line (GL) is discharged toward the base voltage line (GVL) due to the resistance component and the capacitance component appearing at the time of startup. Thus, the falling portion of the high potential gate voltage (Vgh) on the base voltage line (GVL) becomes gentler than the rising portion as shown in FIG. At the same time, the falling part of the scanning signal (SCS) on the gate line (GL) also changes more gradually than the rising part as shown in FIG. As described above, the falling portion of the high potential gate voltage (Vgh) and the scanning signal (SCS) are adjusted more gently than the rising portion, so that the liquid crystal display device can sufficiently suppress the feedthrough voltage (ΔVp). In addition, the response speed increases. The TFT (MN) has an appropriate channel width so that the resistance value of the resistance component and the capacitance of the capacitance component are appropriately set. Further, the TFT (MN) and the base voltage line (GV
During L), a resistor and / or a capacitance for slightly increasing the time constant can be added.

FIG. 11 schematically illustrates an active matrix liquid crystal display according to a fifth embodiment of the present invention. The active matrix liquid crystal display device shown in FIG.
(MN), the resistor (R2) is connected to the second voltage line (SV
L) and the same circuit configuration as the liquid crystal display of FIG. 10 except that it is connected between the ground voltage line (GVL). The resistance (R2) is a switch (5
2) is activated by the high logic state of the gate scanning clock (GSC), the second voltage line (SV
L) and the voltage charged in the gate line (GL) is prevented from leaking. When the switch (52) for controlling one contact is activated, the resistance (R2) changes the voltage on the second voltage line (SVL) and the gate line (GL) toward the base voltage line (GVL). As the discharging time becomes longer, the falling portion of the high potential gate voltage (Vgh) and the scanning signal (SCS) changes in the form of an exponential function. In other words, the resistor (R2) is connected to the second voltage line (SV) when the first contact control switch (52) is activated.
L) and the falling portion of the high potential gate voltage (Vgh) on the gate line (GL) become more gentle than the rising portion as shown in FIG. At the same time, the falling part of the scanning signal (SCS) on the gate line (GL) also changes more gradually than the rising part as shown in FIG. As described above, the falling portion of the high potential gate voltage (Vgh) and the scanning signal (SCS) are adjusted more gently than the rising portion, so that the liquid crystal display device can sufficiently suppress the feedthrough voltage (ΔVp). In addition, the response speed increases.

In the liquid crystal display devices according to the second to fifth embodiments shown in FIGS. 6, 8, 10 and 11, the switching operation of the voltage regulator 46 is controlled by the gate scanning clock (GSC). This eliminates the timing controller (48) in FIG. As a result, the second to fifth illustrated in FIG. 6, FIG. 8, FIG. 10 and FIG.
In the active matrix liquid crystal display device of the embodiment, the circuit configuration is further simplified. In conjunction with this, FIGS.
In the liquid crystal display devices according to the second to fifth embodiments shown in FIGS. 10 and 11, a gate scanning clock (GSC) is used.
Of the liquid crystal cell is 50%, but can be appropriately adjusted within a range where the voltage can be sufficiently charged in the liquid crystal cell.

FIG. 12 shows a scanning signal (SCS) and a data voltage signal (DVS) appearing on a gate line (GL) and a signal line (SL) of an active matrix liquid crystal display according to the first to fifth embodiments of the present invention. Illustrated. The scanning signal (SCS) illustrated in FIG. 12 has a voltage level almost close to the data voltage signal (DVS) at a falling edge. As a result, the liquid crystal display device can sufficiently suppress the feedthrough voltage (ΔVp), and the response speed increases.

FIG. 13 schematically illustrates an active matrix liquid crystal display according to a sixth embodiment of the present invention. The active matrix liquid crystal display of FIG. 13 includes a low potential gate voltage generator (40) and a high potential gate voltage generator (42) connected to the first voltage line (FVL). The low-potential gate voltage generator (40) supplies a low-potential gate voltage (Vgl) whose voltage level is kept constant to n control switches (39) connected to the first voltage line (FVL). High potential gate voltage generator (42)
Generates a pulse-like high-potential gate voltage (Vgh) having first and second high-potential voltages (VDD1, VDD2) alternately as shown in FIG. In order to generate such a high-potential gate voltage (Vgh), the high-potential gate voltage generator (42) includes first and second high-potential voltages (VDh).
D1, VDD2) high-potential voltage generator (54)
And a high potential voltage generator (54) and a second voltage line (S
VL). The first high potential voltage (VDD1) generated by the high potential voltage generator (54) stably maintains a constant voltage level, and the second high potential voltage (VDD2) is higher than the low potential gate voltage (Vgl). Thus, a voltage level lower than the first high potential voltage (VDD1) is stably maintained. These first and second
The high potential voltages (VDD1, VDD2) are supplied to the voltage regulator (5
6). The voltage regulator (56) controls the first and second high potential voltages (VDD1, V1) from the high potential generator (54).
DD2) is alternately supplied to the second voltage line (SVL) to generate a high-potential gate voltage (Vgh) on the second voltage line (SVL) as shown in FIG. To this end, the voltage regulator (56) has a second control switch (5) responsive to a gate scanning clock (GSC).
8). The second control switch (58) is connected to the first scanning switch in the high logic section of the gate scanning clock (GSC).
By supplying the high potential voltage (VDD1) to the second voltage line (SVL), the first high potential voltage (VDD1) appears on the second voltage line (SVL) and the gate line (GL). Alternatively, when the gate scanning clock (GSC) has a low logic, the second control switch (58) supplies the second high potential voltage (VDD2) to the second voltage line (SVL) to supply the second voltage to the second voltage line (SVL). The second high potential voltage (VDD2) appears on the voltage line (SVL) and the gate line (GL). As a result, the high-potential gate voltage (Vgh) sequentially has the first high-potential voltage (VDD1) and the second high-potential voltage (VDD2) for each cycle of the gate scanning clock (GSC).

In the active matrix liquid crystal display of FIG. 13, a gate line (GL) on a liquid crystal panel (30) is provided.
And a gate driver (34) for driving.
The liquid crystal panel (30) includes a pixel (31) connected to the signal line (SL) and the gate line (GL). The pixel (31) adjusts the amount of transmitted light in response to the data voltage signal (DVS) from the signal line (SL).
lc) and a TFT (CMN) for switching a data voltage signal (DVS) supplied to the liquid crystal cell (Clc) from the signal line (SL) in response to a scanning signal (SCS) from the gate line (GL). You. In the pixel (31), a storage capacitor (Cst) has a liquid crystal cell (Clc).
Connected in parallel. The gate driver (34) responds to a gate start pulse (GSP) from the control line (CL) and a gate scanning clock (GSC) from the gate clock line (GCL), and a shift register cell (36A). ) And a first control switch (39) connected between the gate line (GL1). Shift register cell (36
A) outputs the gate start pulse (GSP) to the output terminal (QT) at the rising edge of the gate scanning clock (GSC) as shown in FIG. The first control switch (39) selectively selects one of the low potential and high potential gate voltages (Vgl, Vgh) to the gate line (GL) according to the logic state of the output signal of the shift register cell (36A). Supply. Accordingly, a scanning signal (SCS) having a low potential gate voltage (Vgl) or a high potential gate voltage (Vgh) appears on the gate line (GL). To explain these in detail, the control switch (39) is a shift register cell (36A)
Is high, the high-potential gate voltage (Vgh) having the first and second high-potential voltages (VDD1, VDD2) sequentially is supplied to the gate line (GL), while the shift register cell (36A) If the output signal of ()) has low logic, the low potential gate voltage (Vgl) is supplied to the gate line (GL). As a result, in the gate line (GL), the falling portion changes to a staircase shape as shown in FIG.
A scanning signal (SCS) as at 4 appears. "SCSn" shown in FIG. 14 represents the waveform of the scanning signal supplied to the next gate line.

As described above, since the falling portion of the scanning signal (SCS) changes stepwise, the TFT (CMN) included in the pixel (31) receives the scanning signal (SCS) from the gate line (GL). The start-on state is maintained until the voltage drops below the critical voltage. At this time, the electric charge charged in the liquid crystal cell (Clc) flows to the gate line (GL) side, and at the same time, the TFT (C) is transferred from the signal line (SL).
MN), the liquid crystal cell (Clc) is charged with sufficient charge by the data voltage signal (DVS). As a result, the voltage charged in the liquid crystal cell (Clc) does not decrease. The scanning signal (S) on the gate line (GL)
CS) falls below the critical voltage of the TFT (CMN), the amount of voltage fluctuation at the gate line (GL) is T
Since it is the critical voltage of FT (CMN), the liquid crystal cell (Cl
The charge flowing from c) to the gate line (GL) side is extremely small. As a result, the feedthrough voltage (ΔVp)
Is sufficiently suppressed. Further, flicker and an afterimage do not occur at the image point displayed by the pixel (31).

In this case, the parasitic resistance (Rp) on the gate line (GL) of the liquid crystal panel (30) shown in FIG.
The parasitic capacitance (Cp) does not affect the high-potential gate voltage (Vgh). From such a background, it is understood that the parasitic resistance (Rp) and the parasitic capacitance (Cp) are not illustrated in FIG. FIG. 15 illustrates a scanning signal (SCS) and a data voltage signal (DVS) appearing on a gate line (GL) and a signal line (SL) of an active matrix liquid crystal display according to a sixth embodiment of the present invention. The scanning signal (SCS) shown in FIG.
Has a voltage level almost close to the data voltage signal (DVS) due to the falling edge changing stepwise. As a result, the liquid crystal display device feeds through the voltage (ΔV
p) can be sufficiently suppressed, and the response speed increases.

FIG. 16 shows another embodiment of the voltage regulator (56) shown in FIG. 13 in detail. A voltage controller (56) in FIG. 16 includes a comparator (60) that receives a gate scanning clock (GSC) on the inverting terminal (−) side via a resistor (R3), and an output signal of the comparator (60). And first and second transistors (Q1, Q2) responsive to each other in a complementary manner. The comparator (60) is shown in FIG.
The gate scanning clock (GS
C) and a reference voltage (Vref) from the variable resistor (VR), and a comparison signal whose logic state changes according to the result is generated. To explain this in detail, the comparator (6)
0) supplies a low logic comparison signal to the base terminals of the first and second transistors (Q1, Q2) when the voltage of the gate scanning clock (GSC) is higher than the reference voltage (Vref), while the gate scanning clock (GS). G
SC) is lower than the reference voltage (Vref), a high logic comparison signal is sent to the first and second transistors (Qref).
1, Q2). At this time, the variable resistor (VR) divides a potential difference between the first or second high potential voltage (VDD1 or VDD2) and the base voltage (GND) shown in FIG. 13 and uses the divided voltage as a reference voltage. (V
ref) to the non-inverting terminal (+) of the comparator (60). When the comparator (60) generates a high logic comparison signal, the first transistor (Q1) applies the first high potential voltage (VDD1) from the high potential voltage generator (54) of FIG. 13 to the second voltage line. (SVL). On the other hand, the second transistor (Q2) is connected to the high potential voltage generator (5) shown in FIG. 13 when the comparator (60) generates a low logic comparison signal.
The second high potential voltage (VDD2) from 4) is supplied to the second voltage line (SVL). As a result, the gate scanning clock (GSC) is applied to the second voltage line (SVL).
A high-potential gate voltage (Vgh) shown in FIG. The high-potential gate voltage (Vgh) depends on the logic state of the gate scanning clock (GSC) and the first and second high-potential voltages (VDD1, VDD1).
VDD2). The high-potential gate voltage (Vgh) corresponds to the shift register cell (36A) in FIG.
Responds to the falling edge of the gate scanning clock (GSC). Further, the high potential gate voltage (Vgh) is applied to the first and second transistors (Q1, Q2).
Is changed or the reference voltage (Vref) and the gate scanning clock (GSC) are changed by the comparator (6).
When it is supplied to the inverting and non-inverting terminals (−, +) of (0), respectively, it changes in the same manner as the gate scanning clock (GSC). On the other hand, the second voltage line (SVL)
And a resistor (R4) connected between the inverting terminal (-) of the comparator (60) to feed back the voltage on the second voltage line (SVL) to the inverting terminal (-) of the comparator (60). To make the high-potential gate voltage (Vgh) quickly respond to the gate scanning clock (GSC).

Referring to FIG. 18, a liquid crystal panel (30)
A seventh driver including a data driver (32) for driving the upper signal lines (SL1 to SLm) and a gate driver (34) for driving the gate lines (GL1 to GLn) on the liquid crystal panel (30). 1 illustrates an active matrix liquid crystal display according to an embodiment of the invention.
In the liquid crystal panel 30, pixels 31 connected to the signal lines SL and the gate lines GL are arranged in an active matrix form. Each pixel (31) has a data voltage signal (DVS) from the signal line (SL).
A liquid crystal cell (Clc) that adjusts the amount of transmitted light in response to
Scanning signal (SC) from gate line (GL)
S) in response to the liquid crystal cell (Cl) from the signal line (SL).
c) a TFT (CMN) that switches the data voltage signal (DVS) supplied to c). The pixel (3
1) Each has a storage capacitor (Cst) in the liquid crystal cell (Cl
c) are connected in parallel. This auxiliary capacitance (Cst) buffers the voltage charged in the liquid crystal cell (Clc). The data driver (32) is a gate line (G11 to GLn)
Are sequentially driven to supply a data voltage signal (DVS) to all the signal lines (SL1 to SLm). The gate driver (34) outputs the scanning signal (SC).
S) is sequentially supplied to the gate lines (GL1 to GLm), so that the gate lines (GL1 to GLn) can be sequentially used for each horizontal synchronization period. To this end, the gate driver (34) receives the gate start pulse (GSP) from the control line (CL) and the gate clock line (GC).
L), a shift register (36) responsive to the gate scanning clock (GSC) from the shift register (3).
6) and a level shift (62) connected between the gate lines (GL1 to GLn). The shift register (36) outputs a gate start pulse (GSP) from the control line (CL) to n output terminals (QT1 to QT1).
n), the gate start pulse (GSP) is output to the first output terminal (Q) in response to the gate scanning clock (GSC) in addition to the output to any one of the output terminals.
From T1) to the n-th output terminal (QTn) side. Also, the shift register 36 operates with an integrated circuit driving voltage having 5V corresponding to a logic voltage level. The level shift (62) generates n scanning signals (SCS) by shifting the voltage level of the output signal of the shift register (36). To this end, the level shift (62) is commonly connected to the first voltage line (FVL), and the gate lines (GL1 to GLn).
The n PMOS transistors (M
P1 to MPn) and n NMOS transistors (MN1 to MNn) commonly connected to the second voltage line (SVL) and connected to the gate lines (GL1 to GLn), respectively. .

The low voltage gate voltage (Vgl) generated by the low voltage gate voltage generator (40) is supplied to the first voltage line (FVL). The first to n-th PMOS transistors (MP1 to MPn) are shift registers (36).
Have gate electrodes connected to the respective n output terminals (QT1 to QTn). Similarly, the first to n-th NM
The OS transistors (MN1 to MNn) also have gate electrodes connected to the n output terminals (QT1 to QTn) of the shift register (36). 1st to nth PO
Each of the MS transistors (MP1 to MPn) responds to a signal on an output terminal of the shift register (36) by a first signal.
To the nth NMOS transistors (MN1 to MNn). Shift register (3
6) responding to signals from the output terminals (QT1 to QTn), respectively.
1 to MNn) are sequentially activated for each horizontal synchronization period. As a result, the first to n-th PMOS transistors (MP
1 to MPn) are sequentially activated for each horizontal synchronization period. As a result, the second voltage line (SVL) is sequentially connected to the first to n-th gate lines (GL1 to GLn) for each horizontal synchronization period. The level shift (62) includes n PMOS transistors (MPn + 1 to MP2n) connected in parallel between the second voltage line (SVL) and the high potential voltage generator (44), and the second voltage line (SVL). And a discharge resistor (Rd) connected between the ground line (GNDL). These n PMOS transistors (MPn + 1 to MP2n) are connected to the enable line (EO).
L) In response to the gate output enable signal (GOD) shown in FIG. 19 in common, it is simultaneously activated from the start point of each horizontal synchronization cycle for a period corresponding to half of the horizontal synchronization cycle. When these n PMOS transistors (MPn + 1 to MP2n) are activated, the high potential voltage generator (4
The high potential voltage (VDD) generated in 4) is n PMOs.
The voltage is supplied to one of n gate lines (GL1 to GLn) via a parallel circuit of S transistors (MPn + 1 to MP2n) and a second voltage line (SVL). On the other hand, n PMOS transistors (MPn + 1
To MP2n), the charged voltage on any one of the n gate lines (GL1 to GLn) is grounded via the second voltage line (SVL) and the discharge resistor (Rd). Discharged to the line (GNDL) side. At this time, the discharge speed (ie, time constant) of the voltage on the gate line (GL) is determined by the discharge resistance (Rd), the parasitic capacitance (Cc) and the parasitic resistance (Rc) on the gate line (GL). Thereby, the second voltage line (S
VL), as shown in FIG. 19, in the high logic period of the gate scanning clock (GSC) (that is, the first half cycle of the horizontal synchronizing signal), the high potential voltage level (VDD) is maintained to maintain the gate scanning clock (GSC). In the low logic section, a high-potential gate voltage (Vgh) that decreases exponentially from the high-potential voltage level (VDD) is generated.

The first to n-th gate lines (GL1 to G)
Ln) are sequentially activated by the period of the horizontal synchronization signal. Each of the NMOS transistors (GL1 to GLn) is sequentially activated by the period of the horizontal synchronization signal.
The high potential gate voltage (V) on the second voltage line (SVL) via each of the S transistors (GL1 to GLn)
gh) for one cycle of the horizontal synchronizing signal, and the PMOS transistors (MP1 to MP1) for the remaining period.
n), the low potential gate voltage (Vgl) on the first voltage line (FVL) is input. As a result, the first to n-th gate lines GL1 to GLn receive the scanning signals SCS1 to SCSn shown in FIG. The scanning signal (SCS) maintains a high potential voltage in a high logic section of the gate scanning clock (GSC) (that is, the first half cycle of the horizontal synchronization signal), and maintains a low logic section of the gate scanning clock (GCS) (horizontal synchronization signal). In the latter half period, the voltage decreases exponentially from the high potential voltage to a voltage close to the critical voltage (Vth) of the TFT (CMN) on the liquid crystal panel (30). Also, the scanning signal (SCS) is TF at the start of the next horizontal synchronization cycle.
It drops sharply to a voltage lower than the critical voltage of T (CMN) (that is, a low potential gate voltage (Vgl)). As described above, the falling portion of the scanning signal (SCS) supplied to the gate line (GL) of the liquid crystal panel (30) gradually changes, so that the TFT (CM) included in the pixel (31) is changed.
N) is activated until the voltage of the scanning signal (SCS) from the gate line (GL) falls below the critical voltage. At this time, the charge charged in the liquid crystal cell (Clc) flows to the gate line (GL) side, but the signal line (S
A sufficient charge is charged to the liquid crystal cell (Clc) by the data voltage signal (DVS) from L) through the TFT (CMN). As a result, the voltage charged in the liquid crystal cell (Clc) does not decrease. When the voltage of the scanning signal (SCS) on the gate line (GL) drops below the threshold voltage of the TFT (CMN), the amount of voltage fluctuation on the gate line (GL) is the critical voltage of the TFT (CMN). The charge flowing from the cell (Clc) to the gate line (GL) side is extremely small. As a result, the feedthrough voltage (ΔVp) is sufficiently suppressed. Further, the n PMOS transistors (MPn + 1 to MP2)
n) is a combination of the high-potential voltage generator (44) and the second
The resistance value between the voltage lines (SVL) can be reduced.
Therefore, out of the n PMOS transistors (MPn + 1 to MP2n), n-1 PMOS transistors can be eliminated. In this case, the gate driver (34)
Is simplified. Further, the gate start pulse (GSP) and the gate scanning clock (GS)
C) and the gate enable signal (GOE) are generated by a timing controller (not shown).

FIG. 20 shows a line scanning circuit for driving any one of the gate lines in the active matrix liquid crystal display device shown in FIG. The line scanning circuit shown in FIG. 20 includes a gate driver (34) for driving a gate line (GL) on the liquid crystal panel (30). The liquid crystal panel (30) has a signal line (SL) and a gate line (G
L). Pixel (31)
Is the data voltage signal (DVS) from the signal line (SL)
A liquid crystal cell (Clc) that adjusts the amount of transmitted light in response to
Scanning signal (SC) from gate line (GL)
S) in response to the liquid crystal cell (Cl) from the signal line (SL).
c) a TFT (CMN) that switches the data voltage signal (DVS) supplied to c). The pixel (31)
Is connected in parallel with a liquid crystal cell (Clc). The gate driver (34) is connected to the control line (C
L) and a shift register cell (36) responsive to a gate start pulse (GSP) from the gate clock line (GCL) and a gate scanning clock (GSC) from the gate clock line (GCL).
A) and a level shift cell (62A) connected between the shift register cell (36A) and the gate line (GL)
It consists of. The shift register cell (36A) is shown in FIG.
The gate start pulse (GSP) shown in FIG. 19 is output to the output terminal (QT) side at the rising edge of the gate scanning clock (GSC) shown in FIG. The level shift cell (62A) generates a scanning signal (SCS) by shifting the voltage level of the output signal of the shift register cell (36A). To this end, the level shift cell (62A) includes a first PMOS transistor (MP1) connected between the first voltage line (FVL) and the gate line (GL) on the liquid crystal panel (30), and a second voltage line ( SVL) and a first NMOS transistor MN1 connected between the gate line GL.

The first voltage line (FVL) is supplied with the low potential gate voltage (Vgl) generated by the low potential gate voltage generator (40). The first PMOS transistor (MP1) has a gate electrode connected to the output terminal (QT) of the shift register cell (36A). Similarly, the first NMOS transistor (MN1) has a gate electrode connected to the output terminal (QT) of the shift register cell (36A). The first PMOS transistor (MP1) is complementarily activated with the first NMOS transistor (MN1) in response to a signal on the output terminal of the shift register cell (36A). A first NMOS responsive to a signal from the output terminal (QT) of the shift register cell (36A)
The transistor (MN1) is activated during an arbitrary horizontal synchronization period, while the first PMOS transistor (MP1) is activated during the remaining frame period except for an arbitrary horizontal synchronization period. As a result, the second voltage line (SVL) is connected to the gate line (GL) only during an arbitrary horizontal synchronization period, and the first voltage line (FVL) is connected to the remaining frame excluding the arbitrary horizontal synchronization period. Gate line (GL) during the period
Connected to.

The level shift cell (62A) includes a second PMOS transistor (MP2) connected between the high potential voltage generator (44) and the second voltage line (SVL);
And a discharge resistor (Rd) connected between the second voltage line (SVL) and the ground line (GNDL).
The second PMOS transistor MP2 corresponds to a half of the horizontal synchronization period from the start of each horizontal synchronization period in response to the gate output enable signal GOE shown in FIG. 18 from the enable line EOL. Fired during the period.
When the second PMOS transistor (MP2) is activated, the high potential voltage generator (44) turns on the high potential voltage (VDD).
Is supplied to the gate line (GL) via the second voltage line (SVL). On the other hand, when the second PMOS transistor (MP2) is activated, the voltage charged on the gate line (GL) is discharged to the ground line (GNDL) through the second voltage line (SVL) and the discharge resistor (Rd). Is done. At this time, the discharge speed (ie, time constant) of the voltage on the gate line (GL) is the discharge resistance (Rd), the parasitic capacitance (Cp) and the parasitic resistance (Rp) on the gate line (GL).
p). Accordingly, the second voltage line (SVL) maintains the high potential voltage level (VDD) in the high logic period (ie, the first half cycle of the horizontal synchronization signal) of the gate scanning clock (GSC) illustrated in FIG. In the low logic section of the gate scanning clock (GSC), a high-potential gate voltage (Vgh) that gradually decreases exponentially from the high-potential voltage level (VDD) appears. The gate line (GL) applies a high-potential gate voltage (Vgh) on the second voltage line (SVL) via the first NMOS transistor (MN1) activated during an arbitrary period of the horizontal synchronization signal to the period of the horizontal synchronization signal. During the rest of the period excluding the above, the low potential gate voltage (V) on the first voltage line (FVL) via the first PMOS transistor (MP1)
gl). As a result, one of the scanning signals (SCS1 to SCSn) shown in FIG. 19 is supplied to the gate line (GL). The scanning signal (SCS) is a gate scanning clock (GS).
C) high logic section (that is, the first half cycle of the horizontal synchronization signal)
In the low logic period of the gate scanning clock (GSC) (in the second half cycle of the horizontal synchronization signal), the high potential voltage is maintained from the high potential voltage to the TF on the liquid crystal panel (30).
It decreases exponentially to a voltage close to the critical voltage (Vth) of T (CMN).

Also, the scanning signal (SCS) drops sharply to a voltage lower than the critical voltage of the TFT (CMN) (ie, a low potential gate voltage (Vgl)) at the start of the next horizontal synchronization cycle. As described above, the scanning signal (SCS) supplied to the gate line (GL) of the liquid crystal panel (30).
The falling portion of the pixel gradually changes, and the pixel (31)
Are activated until the voltage of the scanning signal (SCS) from the gate line (GL) falls below its own threshold voltage. At this time, the charges charged in the liquid crystal cell (Clc) flow to the gate line (GL) side, and sufficient charges are generated from the signal line (SL) by the data voltage signal (DVS) passing through the TFT (CMN). ) Is charged. As a result, the voltage charged in the liquid crystal cell (Clc) does not decrease. When the voltage of the scanning signal (SCS) on the gate line (GL) drops below the critical voltage of the TFT (CMN), the amount of voltage fluctuation on the gate line (GL) becomes the maximum TFT (CMN).
, The amount of charge flowing from the liquid crystal cell (Clc) to the gate line (GL) side is extremely small. As a result, the feedthrough voltage (ΔVp) is sufficiently suppressed.

FIG. 21 schematically illustrates an active matrix liquid crystal display according to an eighth embodiment of the present invention. The active matrix liquid crystal display device shown in FIG.
And the second voltage line (SVL) and the high-potential voltage generator (4
4) instead of the n PMOS transistors (MPn + 1 to MP2n) connected in parallel and the discharge resistor (Rd) connected between the second voltage line (SVL) and the ground line (GNDL). Potential voltage generator (44)
It has the same circuit configuration as the active matrix liquid crystal display of FIG. 18 except that it has a voltage regulator (64) connected between the active matrix liquid crystal display and the second voltage line (SVL).
The voltage regulator (64) is a gate clock line (GCL)
The high-potential voltage generator (44) responds to the gate scanning clock (GSC) from the second voltage line (SV).
L) to provide a discharge path to the second voltage line (SVL). To explain this in detail, the voltage regulator (6)
4) When the gate scanning clock (GSC) has a high logic value, the high potential voltage (VDD) from the high potential generator (44) is applied to the second voltage line (SVL) and n NMOS transistors (MN1 to MN1). MNn) and transmitted to the gate line (GL) side via any one of them. On the other hand, when the gate scanning clock (GSC) has a low logic value, the voltage regulator (64) provides a discharge path to the second voltage line (SVL) to provide a gate line (GSL).
The voltage charged on L1 to GLn is discharged through the second voltage line SVL and the discharge path. At this time, the discharge rate of the voltage on the gate line (GL) (ie,
The time constant is determined by the resistance value of the discharge path, the parasitic capacitance (Cc) and the parasitic resistance (Rc) on the gate line (GL). As a result, the voltage regulator (64) operates the gate scanning clock (G) as shown in FIG.
SC) in the high logic section (that is, the first half cycle of the horizontal synchronization signal), the high potential voltage level (VDD) is maintained, and in the low logic section of the gate scanning clock (GSC), the high potential voltage level (VDD) is exponentially changed from the high potential voltage level (VDD). The high-potential gate voltage (Vgh) gradually decreasing to the second voltage line (S
VL).

The first to n-th gate lines (GL1 to GL1)
To GLn) via the NMOS transistors (MN1 to MNn) which are sequentially activated by the period of the horizontal synchronizing signal, respectively. During the remaining period, the low-potential gate voltage (Vgl) on the first voltage line (FVL) is input via the PMOS transistors (MP1 to MPn). As a result, the first to n-th gate lines (GL1 to GLn) are connected to the scanning signal (SC) shown in FIG.
S1 to SCSn). The scanning signal (SCS) maintains a high potential voltage in the high logic section of the gate scanning clock (GSC) (that is, the first half cycle of the horizontal synchronizing signal), and the gate scanning clock (GSC).
In the low logic section of CS) (the latter half cycle of the horizontal synchronizing signal), the TFT (CM) on the liquid crystal panel (30) changes from the high potential voltage.
N) exponentially decreases to a voltage close to the critical voltage (Vth). Also, the scanning signal (SCS) drops sharply to a voltage lower than the critical voltage of the TFT (CMN) (ie, a low potential gate voltage (Vgl)) at the start of the next horizontal synchronization cycle.

As described above, the scanning signal (SC) supplied to the gate line (GL) of the liquid crystal panel (30).
Since the falling portion of S) changes gradually, the pixel (3)
The TFT (CMN) included in 1) is a gate line (G
It is activated until the voltage of the scanning signal (SCS) from L) falls below the critical voltage. At this time, the electric charge charged in the liquid crystal cell (Clc) flows to the gate line (GL) side, but the charge is transferred from the signal line (SL) to the TFT (CMN).
The liquid crystal cell (Clc) is charged with a sufficient charge by the data voltage signal (DVS) passing through. by this,
The voltage charged in the liquid crystal cell (Clc) does not decrease. The scanning signal (SC) on the gate line (GL)
When the voltage of S) falls below the critical voltage of the TFT (CMN), the amount of voltage fluctuation at the gate line (GL) is the maximum TF.
Liquid crystal cell (Clc) because it is the critical voltage of T (CMN)
The amount of charge flowing from the gate line (GL) to the gate line (GL) becomes extremely small. As a result, the feedthrough voltage (ΔVp) is sufficiently suppressed.

FIG. 22A shows a waveform of a scanning signal provided by an active matrix liquid crystal display according to the present invention, and FIG. 22B shows a scanning signal provided by a conventional active matrix liquid crystal display. The scanning signal of FIG. 22a differs from the scanning signal of FIG. 22b in that it has an exponentially decreasing falling edge. Accordingly, in the active matrix liquid crystal display according to the present invention, the potential difference between the gate electrode and the source electrode of the TFT (CMN) when the TFT (CMN) is turned off is reduced. Therefore, the charge discharged from the liquid crystal cell when the TFT (CMN) is turned off is significantly reduced. As a result, the feedthrough voltage (ΔV
p) is reduced and flicker is significantly reduced.
FIG. 23a shows the current change when the TFT (CMN) is activated in the active matrix liquid crystal display device according to the present invention, and FIG. 23b shows the current change when the TFT (CMN) is activated in the conventional active matrix liquid crystal display device. Respectively. FIGS. 23A and 23B show that the active matrix liquid crystal display device according to the present invention can greatly suppress the transient noise component as compared with the conventional liquid crystal display device.

FIG. 24 illustrates an embodiment of the voltage regulator (64) shown in FIG. 20 in detail. FIG.
In the voltage regulator (64), the high potential voltage line (V
DDL) and a first resistor (R1, R2) connected in series between a ground line (GNDL) and a first node (N
1) and a third voltage connected between the second voltage line (SVL).
A resistor (R3). First and second resistors (R1,
R2) divides the high-potential voltage (VDD) on the high-potential voltage line (VDDL) so that the divided voltage appears on the first node (N1). The third resistor (R3) limits the amount of current between the first node (N1) and the second voltage line (SVL). The voltage regulator (64) includes a high potential voltage line (VDDL), a first transistor (TR1) connected between the first and second nodes (N1, N2), a second resistor (R2), and a ground line ( And a second transistor (TR2) connected between the first and second transistors (GNDL). First
The transistor (TR1) selectively transmits the high potential voltage (VDD) on the high potential voltage line (VDDL) to the first node (N1) in response to the voltage on the second node (N1).

More specifically, the first transistor TR1 is activated when the voltage on the second node N2 is lower than the threshold voltage (ie, 0.7V), and the first transistor TR1 is turned on when the voltage on the first node N1 is lower than 0.7V. The voltage maintains the high potential voltage level. Second
When the voltage on the node (N2) is higher than the threshold voltage, the first transistor (TR1) is turned off to open the high potential voltage line (VDDL) and the first node (N1). For this purpose, a P-type junction transistor is used as the first transistor (TR1). The voltage on the second node (N2) is changed by a third transistor (TR3) having a base connected to the fourth node (N4). The third transistor (TR3) is connected to the fourth node (N
4) is activated when the gate scanning clock (GSC) from the high potential voltage line (V
DDL) to the fourth resistor (R4), the second node (N2),
A current path is formed to the ground line (GNDL) via the fifth resistor (R5), its own collector and emitter. In this case, a voltage lower than the threshold voltage of the transistor TR appears at the second node N2. Alternatively, when the gate scanning clock (GSC) on the fourth node (N4) has a low logic, the third transistor (TR3) is turned off and the second transistor (TR3) is turned off.
The voltage of 2) maintains the high potential voltage level. On the other hand, the second
The transistor TR2 selectively connects the second resistor R2 to the ground line in response to a voltage on the third node N3. At this time, the high potential gate voltage (Vgh) on the second voltage line (SVL) is equal to the third resistor (R3), the first node (N1), the second resistor (R2), and the spare transistor (TR).
It is discharged to the ground line (GNDL) side via the collector and the emitter of 2).

On the other hand, if the voltage on the third node N3 is lower than the threshold voltage, the second transistor TR2 is turned off, and the second resistor R2 and the ground line GND are turned off.
L) is released. For this purpose, an N-type junction transistor (TR) is used in the second transistor (TR). The voltage on the third node (N3) is
4) having a base connected to the fourth transistor (T)
It changes depending on the operation state of R4). The fourth transistor TR4 is activated when the gate scanning clock GSC from the fourth node N4 has a high logic value, and connects the third node N3 to the ground line GNDL. Accordingly, the ground voltage (GND) appears at the third node (N3). In contrast, the gate scanning clock (GS) on the fourth node (N4) is different.
C) has a high logic value, the fourth transistor (T
R4) is turned off, and the third node N3 and the ground line GNDL are opened.

At this time, the high potential voltage (VDD) on the high potential voltage line (VDDL) is charged to the third node (N3) via the sixth resistor (R6). Therefore, a high potential voltage (VDD) appears at the third node (N3). As a result, the voltage on the second node (N2) and the third node (N3)
The upper voltage varies in the same manner. These second and third
When the voltages on the nodes (N2, N3) change in the same manner, the first and second transistors (TR1, TR2) are driven complementarily. In other words, the first transistor (TR1) is connected to the gate scanning clock (GSC)
, The second transistor TR2 is activated during the low logic period of the gate scanning clock GSC. Thereby, the first node (N
2) and the voltage on the second voltage line (SVL) is a high potential voltage (VDD) during the high logic period of the gate scanning clock (GSC), and the gate scanning clock (G
SC) in the low logic section, the high potential voltage level (VDD)
Exponentially down to the divided voltage level. As a result, a high potential gate voltage (Vgh) having the waveform shown in FIG. 18 appears on the second voltage line (svl). The gate scanning clock (GSC) is supplied from the gate clock line (GCL) to the fourth node (N4) via the seventh resistor (R7). Seventh resistor (R7)
Is from the gate clock line (GCL) to the fourth node (N
4) Limit the current flowing to the side. The second and third resistors (R
2, R3) is the voltage of the voltage on the gate line (GL) together with the parasitic capacitance (Cp) and the parasitic resistance (Rp) on the gate line (GL) shown in FIG. 20 when the second transistor (TR2) is activated. Determine the discharge rate.

FIG. 25 schematically illustrates a TAB type liquid crystal display device according to the present invention. In the TAB type liquid crystal display device of FIG. 25, a liquid crystal panel (30) has a liquid crystal layer (3) sealed between an upper glass substrate (30A) and a lower glass substrate (30B).
0C). This liquid crystal panel (30) is an FPC
(Flexible Printed Circuit) film (66) connected to PCB (Printed Circuit Board) module (68). PCB module (68) is P
A control circuit unit (72) mounted on the upper surface of the CB (70),
It has low and high potential gate voltage generators (40, 42). The FPC film (66) has a lower glass substrate (30
B) One step connected to the pad area and PCB (70)
It has another step connected to the edge of the bottom surface of. Also, FPC
The data driver (32) and / or the gate driver (34) are grounded in the middle of the film (66). Data driver (32) and / or gate driver (34)
The liquid crystal panel (30) and the PCB module (68) are connected by the PC film (66). Such F
The PC film (66) includes a first conductive layer pattern (67A) for electrically connecting the liquid crystal panel (30) to the data driver (32) and / or the gate driver (34), and the data driver (32) and / or the gate. Driver (3
4) has a second conductive layer pattern (67B) for electrically connecting the second conductive layer to the PCB module (68). These first and second conductive layer patterns (67A, 67B) have the first and second protective films (69A, 69) exposed at both ends.
B) wrapped.

FIG. 26 shows a COG (Chips On) according to the present invention.
1 schematically illustrates a (Glass) type liquid crystal display device. FIG.
COG type liquid crystal display device has an upper glass substrate (30A)
And a liquid crystal layer (30C) sealed between the lower glass substrate (30B). This liquid crystal panel (30)
PC (Flexible Printed Circuit) film (66)
Connected to a PCB (Printed Circuit Board) module (68). The PCB module (68) includes a control circuit (7) mounted on the upper surface of the PCB (70).
2) low and high potential gate voltage generators (40, 4
2). The data driver (32) and / or the gate driver (34) are mounted on the pedestal area of the lower glass substrate (30B). These data driver (32) and / or gate driver (34) are connected to the liquid crystal panel (30) and the PCB by the FPC film (66).
Connected to module (68). FPC film (6
6) is a data driver (32) and a gate driver (3)
4) is connected to the PCB module (68) on which is mounted. To this end, the FPC film (66) is connected to the one-step portion connected to the pedestal area of the lower glass substrate (30B) by the PC.
It has another step connected to the edge of the bottom surface of B (70). Such an FPC film (66) is provided with a data driver (3).
2) and / or a conductive layer pattern (67) for electrically connecting the liquid crystal panel (30) on which the gate driver (34) is mounted and the PCB module (68). The conductive layer pattern (67) is wrapped by the protective film (69) so that the end is exposed.

The low-potential gate voltage generator and the high-potential gate voltage generator disclosed in the present invention are located in the PCB module, and the voltage controller can be arranged in various forms on the LCD module. First, a voltage controller can be located on the PCB module. In other words, the voltage controller, the high-potential gate voltage generator and the low-potential gate voltage generator are all formed on the PCB module. Such a circuit structure is similar to that of the normal gate driver IC shown in FIG.
th). Therefore, the object of the present invention is achieved without modifying the gate driver IC. Next, the voltage controller is mounted in the gate driver IC. The voltage controller mounted in the gate driver IC may be connected between the high-potential gate voltage generator and the vapor as shown in FIG. In a different manner, the voltage controller included in the gate driver IC may be connected between one high-potential voltage generator and multiple bumpers as shown in FIGS. The gate driver IC including the voltage controller is PCB and the voltage controller is PC
The number of components of the LCD module can be reduced as compared with the case where the components are arranged on the B module, and the cost of components can be further reduced.

[0045]

As described above, in the active matrix liquid crystal display device according to the present invention, the falling portion of the scanning signal is linear, exponential, or staircase by supplying a high potential gate voltage to the gate driver level shift in an AC form. It changes in any one of the functions. Thus, in the active matrix liquid crystal display device according to the present invention, the feedthrough voltage (ΔVp) is sufficiently suppressed,
Further, generation of flicker and afterimages is suppressed. Further, in the active matrix liquid crystal display device according to the present invention, the circuit configuration is extremely simplified.

In the active matrix liquid crystal display device according to the present invention, the falling portion of the high-potential gate voltage changes more gently than the rising portion, so that the falling portion of the scanning signal supplied to the gate line is more gradual than the rising portion. Changes to As a result, in the active matrix liquid crystal display device according to the present invention, it is needless to say that flicker and afterimages do not occur, and the response speed is further increased.

From the above description, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but must be defined by the claims.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a conventional liquid crystal display device.

FIG. 2 is a diagram illustrating a waveform of a scanning signal whose falling portion changes gradually.

FIG. 3 is a diagram illustrating a conventional liquid crystal display device using a scanning signal illustrated in FIG. 2B.

FIG. 4 is a view illustrating a structure of a general liquid crystal display device.

FIG. 5 is a diagram schematically illustrating an active matrix liquid crystal display according to a first embodiment of the present invention.

FIG. 6 is a diagram schematically illustrating an active matrix liquid crystal display according to a second embodiment of the present invention.

FIG. 7 is an output waveform diagram for an important part shown in FIG. 6;

FIG. 8 is a diagram schematically illustrating an active matrix liquid crystal display according to a third embodiment of the present invention.

FIG. 9 is an output waveform diagram for an important part shown in FIG. 8;

FIG. 10 is a diagram schematically illustrating an active matrix liquid crystal display according to a fourth embodiment of the present invention.

FIG. 11 is a diagram schematically illustrating an active matrix liquid crystal display according to a fifth embodiment of the present invention.

FIG. 12 is a waveform diagram of a scanning signal and a data voltage signal appearing on a gate line and a signal line of a liquid crystal display according to the first to fifth embodiments of the present invention, respectively.

FIG. 13 is a diagram schematically illustrating an active matrix liquid crystal display according to a sixth embodiment of the present invention.

FIG. 14 is an output waveform diagram for an important part shown in FIG.

FIG. 15 is a waveform diagram of a scanning signal and a data voltage signal appearing on a gate line and a signal line of the liquid crystal panel shown in FIG.

FIG. 16 is a view illustrating another embodiment of the voltage regulator illustrated in FIG. 13;

FIG. 17 is an input and output waveform diagram of the voltage regulator shown in FIG. 16;

FIG. 18 is a diagram schematically illustrating an active matrix liquid crystal display according to a seventh embodiment of the present invention.

FIG. 19 is an output waveform diagram for an important part shown in FIG. 18;

20 is a diagram illustrating a line scanning circuit for driving one gate line in the liquid crystal display device illustrated in FIG. 18;

FIG. 21 is a view schematically illustrating an active matrix liquid crystal display according to an eighth embodiment of the present invention.

FIG. 22 is a waveform diagram of a scanning signal according to the present invention a and a conventional b active matrix liquid crystal display device.

FIG. 23 shows a TFT (CMN) using an active matrix liquid crystal display device according to the present invention a and the conventional b).
5 is a diagram illustrating a change in current when the device is activated.

FIG. 24 is a diagram illustrating the voltage regulator shown in FIG. 21 in detail.

FIG. 25 is a view illustrating a tap-type liquid crystal display device according to the present invention.

FIG. 26 is a view illustrating a COG type liquid crystal display device according to the present invention.

[Explanation of symbols]

10: Liquid crystal panel 11, 31: Pixel 12, 32: Data driver 14, 34: Gate driver 3, 16, 36: Shift register 118, 38, 62: Level shift 5, 6, 9, 19: Inverter 20: Scanning Driver cell 22: Integrator 30A: Upper glass substrate 30B: Lower glass substrate 30C: Liquid crystal layer 36A: Shift register cell 39, 58: Control switch 40: Low potential gate voltage generator 42: High potential gate voltage generator 44, 54: high-potential voltage generator 46, 56, 64: voltage regulator 48: timing controller 50: switch for 2-contact control 52: switch for 1-contact control 60: comparator 62A: level shift cell 66: FPC film 67, 67A, 67B: Conductive layer pattern 68: PCB module 69, 69A, 69
B: Protective film 70: PCB 72: Control circuit section SL, SL1 to SLm: Signal line GL, GL1 to GLm: Gate line Clc: Liquid crystal cell CMN: Thin film transistor (TFT) CL: Control line GCL: Gate clock line FVL: First One voltage line SVL: Second voltage line Cst: Auxiliary capacitance MP1 to MPn, MPn + 1 to MP2n: PMOS
Transistors MN1 to MNn: NMOS transistors Rp, Rc: parasitic resistance Cp, Cc: parasitic capacitance SCL: synchronization control line DCL: data clock line GVL: base voltage line Q1, Q2: transistor VR: variable resistance GNDL: ground line

Claims (16)

[Claims] A plurality of pixels arranged in a matrix and including switch transistors each having a gate electrode and a second electrode connected to the first electrode and the pixel electrode; and one of the plurality of transistors. A plurality of data signal lines respectively connected to the first electrode corresponding to the plurality of transistors; a plurality of gate signal lines connected to the gate electrode corresponding to one of the plurality of transistors; A gate driver connected to a line, receiving first and second voltages, and outputting one of the first and second voltages so that the gate signal lines are sequentially driven; An active matrix, wherein the first voltage changes before the continuous gate signal line is activated. The liquid crystal display device. 2. The active matrix liquid crystal display according to claim 1, wherein the first voltage drops before the continuous gate signal line is activated. 3. The active matrix liquid crystal display device according to claim 1, wherein said first voltage drops exponentially. 4. The active matrix liquid crystal display device according to claim 1, wherein said first voltage drops linearly. 5. The active matrix liquid crystal display device according to claim 1, wherein said first voltage drops stepwise. 6. The active matrix liquid crystal display device according to claim 1, wherein a minimum value of said first voltage is higher than a maximum value of said second voltage. 7. The gate driver includes: a shift register that generates a scanning signal supplied to each of the gate lines; and a voltage level of each of the scanning signals from the shift register using the first and second voltages. 2. The active matrix according to claim 1, further comprising a level shifter for shifting, and a voltage regulator for changing a first voltage supplied to the level shifter before the scanning signal is disabled. Liquid crystal display. 8. The voltage regulator includes a switch for cutting off the first voltage supplied to the level shift before the scanning signal is disabled, and the scanning signal is cut off by the switch. 8. The active matrix liquid crystal display device according to claim 7, further comprising: a discharge path provided to the level shift during the operation. 9. The active matrix liquid crystal display device according to claim 8, wherein said switch responds to a gate scan clock together with said shift register. 10. The apparatus according to claim 8, further comprising a timing controller for controlling said switch.
An active matrix liquid crystal display device as described in the above. 11. An input terminal for inputting a first voltage, a first resistor connected between the input terminal and the input terminal for the level shift, and an input terminal for the level shift. A second resistor and a first control switch connected in series between the first resistor and a ground voltage line; and a second control connected in parallel with the first resistor and driven complementarily to the first control switch. 8. An active matrix liquid crystal display device according to claim 7, further comprising a switch for use in said active matrix liquid crystal display device. 12. The active matrix liquid crystal display device according to claim 7, wherein said shift register and said level shift are manufactured by one integrated circuit chip. 13. The active matrix liquid crystal display device according to claim 7, wherein said shift register, said level shifter, and said voltage regulator are manufactured on one integrated circuit chip. 14. A pixel having a thin film transistor connected to the gate line and the signal line in addition to being located at an intersection of the gate line and the signal line;
A method of driving a liquid crystal display device including a gate driver having a shift register in addition to being connected to the gate line, inputting a second voltage that changes periodically with a first voltage; Supplying the second voltage to the gate line via the switch; supplying the first voltage to the gate line via the switch; and controlling the switch element by the shift register. And a driving method of the active matrix liquid crystal display device, wherein a minimum value of the second voltage is higher than a maximum value of the first voltage. 15. The device of claim 14, wherein the first voltage is supplied to the gate line during a period in which the thin film transistor connected to the gate line is activated.
The driving method of the active matrix liquid crystal display device described in the above. 16. The method of claim 14, wherein the shift register operates at a driving voltage corresponding to a logic voltage level.