GB2298959B - Method of fabricating metallized substrates using an organic etch block layer - Google Patents

Method of fabricating metallized substrates using an organic etch block layer

Info

Publication number
GB2298959B
GB2298959B GB9603414A GB9603414A GB2298959B GB 2298959 B GB2298959 B GB 2298959B GB 9603414 A GB9603414 A GB 9603414A GB 9603414 A GB9603414 A GB 9603414A GB 2298959 B GB2298959 B GB 2298959B
Authority
GB
United Kingdom
Prior art keywords
block layer
metallized substrates
etch block
organic etch
fabricating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9603414A
Other languages
English (en)
Other versions
GB9603414D0 (en
GB2298959A (en
Inventor
Philip A Trask
Vincent A Pillai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co, Raytheon Co filed Critical Hughes Aircraft Co
Publication of GB9603414D0 publication Critical patent/GB9603414D0/en
Publication of GB2298959A publication Critical patent/GB2298959A/en
Application granted granted Critical
Publication of GB2298959B publication Critical patent/GB2298959B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/02—Local etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB9603414A 1995-03-14 1996-02-19 Method of fabricating metallized substrates using an organic etch block layer Expired - Fee Related GB2298959B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/403,610 US5474956A (en) 1995-03-14 1995-03-14 Method of fabricating metallized substrates using an organic etch block layer

Publications (3)

Publication Number Publication Date
GB9603414D0 GB9603414D0 (en) 1996-04-17
GB2298959A GB2298959A (en) 1996-09-18
GB2298959B true GB2298959B (en) 1999-03-24

Family

ID=23596399

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9603414A Expired - Fee Related GB2298959B (en) 1995-03-14 1996-02-19 Method of fabricating metallized substrates using an organic etch block layer

Country Status (5)

Country Link
US (1) US5474956A (https=)
JP (1) JP2774092B2 (https=)
FR (1) FR2732161B1 (https=)
GB (1) GB2298959B (https=)
TW (1) TW300324B (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5538078A (en) * 1994-04-08 1996-07-23 Nippondenso Co., Ltd. Aluminum-containing metal composite material and process for producing same
US6258732B1 (en) 1999-02-04 2001-07-10 International Business Machines Corporation Method of forming a patterned organic dielectric layer on a substrate
DE10236466A1 (de) * 2002-08-08 2004-02-19 Siemens Ag Verfahren zur Herstellung von hochfrequenztechnisch verwend-baren elektrischen Leitungsstrukturen
JP4851465B2 (ja) 2004-11-08 2012-01-11 フレッシュポイント・ホールディングス・ソシエテ・アノニム 時間温度指示装置
US7675151B1 (en) * 2005-06-01 2010-03-09 Rockwell Collins, Inc. Silicon-based packaging for electronic devices
AU2009256212B2 (en) * 2008-06-04 2015-12-10 Jp Laboratories Inc. A monitoring system based on etching of metals

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
JPS6386550A (ja) * 1986-09-30 1988-04-16 Pioneer Electronic Corp 多層配線層の形成方法
US5236551A (en) * 1990-05-10 1993-08-17 Microelectronics And Computer Technology Corporation Rework of polymeric dielectric electrical interconnect by laser photoablation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS556833A (en) * 1978-06-29 1980-01-18 Nippon Mektron Kk Cirucit board and method of manufacturing same
US4606998A (en) * 1985-04-30 1986-08-19 International Business Machines Corporation Barrierless high-temperature lift-off process
JPS62117356A (ja) * 1985-11-18 1987-05-28 Sumitomo Electric Ind Ltd 半導体装置用配線基板およびその製造方法
JPS62149136A (ja) * 1985-12-23 1987-07-03 Seiko Epson Corp 半導体装置の製造方法
JPS63226931A (ja) * 1987-03-17 1988-09-21 Nec Corp 半導体装置の製造方法
JP2503565B2 (ja) * 1988-01-21 1996-06-05 三菱電機株式会社 半導体装置の製造方法
JPH02202030A (ja) * 1989-01-31 1990-08-10 Nec Corp 半導体装置の製造方法
US5034091A (en) * 1990-04-27 1991-07-23 Hughes Aircraft Company Method of forming an electrical via structure
US5114757A (en) * 1990-10-26 1992-05-19 Linde Harold G Enhancement of polyimide adhesion on reactive metals
US5194928A (en) * 1991-01-14 1993-03-16 International Business Machines Corporation Passivation of metal in metal/polyimide structure
US5242864A (en) * 1992-06-05 1993-09-07 Intel Corporation Polyimide process for protecting integrated circuits
US5364493A (en) * 1993-05-06 1994-11-15 Litel Instruments Apparatus and process for the production of fine line metal traces

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
JPS6386550A (ja) * 1986-09-30 1988-04-16 Pioneer Electronic Corp 多層配線層の形成方法
US5236551A (en) * 1990-05-10 1993-08-17 Microelectronics And Computer Technology Corporation Rework of polymeric dielectric electrical interconnect by laser photoablation

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan Section E:E-652 Vol. 12 No.322 page 26 & JP63086550 *

Also Published As

Publication number Publication date
US5474956A (en) 1995-12-12
FR2732161B1 (fr) 1998-04-03
JP2774092B2 (ja) 1998-07-09
FR2732161A1 (fr) 1996-09-27
GB9603414D0 (en) 1996-04-17
TW300324B (https=) 1997-03-11
JPH08274452A (ja) 1996-10-18
GB2298959A (en) 1996-09-18

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20040219