GB2226446B - Method of forming low-resistance contacts to doped regions in very large scale integrated devices - Google Patents

Method of forming low-resistance contacts to doped regions in very large scale integrated devices

Info

Publication number
GB2226446B
GB2226446B GB8921421A GB8921421A GB2226446B GB 2226446 B GB2226446 B GB 2226446B GB 8921421 A GB8921421 A GB 8921421A GB 8921421 A GB8921421 A GB 8921421A GB 2226446 B GB2226446 B GB 2226446B
Authority
GB
United Kingdom
Prior art keywords
large scale
doped regions
scale integrated
integrated devices
forming low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB8921421A
Other languages
English (en)
Other versions
GB2226446A (en
GB8921421D0 (en
Inventor
Dae-Je Jin
Chang-Hyun Kim
Chul-Jin Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB8921421D0 publication Critical patent/GB8921421D0/en
Publication of GB2226446A publication Critical patent/GB2226446A/en
Application granted granted Critical
Publication of GB2226446B publication Critical patent/GB2226446B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H10P14/414—Deposition of metallic or metal-silicide materials of metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/416—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4451—Semiconductor materials, e.g. polysilicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
GB8921421A 1988-12-24 1989-09-22 Method of forming low-resistance contacts to doped regions in very large scale integrated devices Expired - Lifetime GB2226446B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880017435A KR930004295B1 (ko) 1988-12-24 1988-12-24 Vlsi 장치의 n+ 및 p+ 저항영역에 저저항 접속방법

Publications (3)

Publication Number Publication Date
GB8921421D0 GB8921421D0 (en) 1989-11-08
GB2226446A GB2226446A (en) 1990-06-27
GB2226446B true GB2226446B (en) 1993-02-24

Family

ID=19280663

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8921421A Expired - Lifetime GB2226446B (en) 1988-12-24 1989-09-22 Method of forming low-resistance contacts to doped regions in very large scale integrated devices

Country Status (6)

Country Link
US (1) US5070038A (enExample)
JP (1) JP2528961B2 (enExample)
KR (1) KR930004295B1 (enExample)
DE (1) DE3908676A1 (enExample)
FR (1) FR2641126A1 (enExample)
GB (1) GB2226446B (enExample)

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US5629218A (en) * 1989-12-19 1997-05-13 Texas Instruments Incorporated Method for forming a field-effect transistor including a mask body and source/drain contacts
KR940008936B1 (ko) * 1990-02-15 1994-09-28 가부시끼가이샤 도시바 고순도 금속재와 그 성질을 이용한 반도체 장치 및 그 제조방법
US5288664A (en) * 1990-07-11 1994-02-22 Fujitsu Ltd. Method of forming wiring of semiconductor device
KR920010759A (ko) * 1990-11-16 1992-06-27 원본미기재 저 저항 접점을 제조하는 방법
EP0496169A1 (en) * 1991-01-25 1992-07-29 AT&T Corp. Method of integrated circuit fabrication including filling windows with conducting material
KR100228619B1 (ko) * 1991-03-05 1999-11-01 아치 케이. 말론 자기-정합 접점 형성 방법 및 구조
US5278096A (en) * 1991-12-23 1994-01-11 At&T Bell Laboratories Transistor fabrication method
US5416034A (en) * 1993-06-30 1995-05-16 Sgs-Thomson Microelectronics, Inc. Method of making resistor with silicon-rich silicide contacts for an integrated circuit
JP2699839B2 (ja) * 1993-12-03 1998-01-19 日本電気株式会社 半導体装置の製造方法
US6200871B1 (en) * 1994-08-30 2001-03-13 Texas Instruments Incorporated High performance self-aligned silicide process for sub-half-micron semiconductor technologies
GB2319658B (en) * 1996-09-21 2001-08-22 United Microelectronics Corp Method of fabricating a word line
TW316326B (en) * 1996-09-21 1997-09-21 United Microelectronics Corp Manufacturing method of word line
JP3413078B2 (ja) * 1997-10-06 2003-06-03 キヤノン株式会社 光電変換装置と密着型イメージセンサ
US6048791A (en) * 1998-03-31 2000-04-11 Kabushiki Kaisha Toshiba Semiconductor device with electrode formed of conductive layer consisting of polysilicon layer and metal-silicide layer and its manufacturing method
JP2001068670A (ja) * 1999-08-30 2001-03-16 Nec Corp 半導体装置の製造方法
JP4209178B2 (ja) * 2002-11-26 2009-01-14 新光電気工業株式会社 電子部品実装構造及びその製造方法
US7407882B1 (en) 2004-08-27 2008-08-05 Spansion Llc Semiconductor component having a contact structure and method of manufacture
US8018015B2 (en) * 2005-06-29 2011-09-13 Micron Technology, Inc. Buried conductor for imagers

Citations (4)

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EP0128304A1 (en) * 1983-05-06 1984-12-19 Texas Instruments Incorporated Method of forming a metallic silicide
EP0211318A1 (de) * 1985-07-29 1987-02-25 Siemens Aktiengesellschaft Verfahren zum selektiven Auffüllen von in Isolationsschichten geätzten Kontaktlöchern mit metallisch leitenden Materialien bei der Herstellung von höchstintegrierten Halbleiterschaltungen sowie eine Vorrichtung zur Durchführung des Verfahrens
EP0248445A2 (en) * 1986-06-06 1987-12-09 Hitachi, Ltd. Semiconductor device having a diffusion barrier and process for its production
EP0286182A1 (en) * 1987-04-08 1988-10-12 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising a titanium disilicide layer

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US4364166A (en) * 1979-03-01 1982-12-21 International Business Machines Corporation Semiconductor integrated circuit interconnections
JPS57186341A (en) * 1981-05-13 1982-11-16 Hitachi Ltd Semiconductor device
US4359490A (en) * 1981-07-13 1982-11-16 Fairchild Camera & Instrument Corp. Method for LPCVD co-deposition of metal and silicon to form metal silicide
JPS59150421A (ja) * 1983-02-10 1984-08-28 Toshiba Corp 半導体装置の製造方法
GB2139420B (en) * 1983-05-05 1987-04-29 Standard Telephones Cables Ltd Semiconductor devices
JPS60143648A (ja) * 1983-08-23 1985-07-29 Nec Corp 半導体装置の製造方法
JPS60119750A (ja) * 1983-12-02 1985-06-27 Hitachi Ltd 半導体装置の製造方法
JPS60193380A (ja) * 1984-03-15 1985-10-01 Nec Corp 半導体装置の製造方法
US4619035A (en) * 1984-06-23 1986-10-28 Nippon Gakki Seizo Kabushiki Kaisha Method of manufacturing a semiconductor device including Schottky barrier diodes
US4720908A (en) * 1984-07-11 1988-01-26 Texas Instruments Incorporated Process for making contacts and interconnects for holes having vertical sidewalls
JPS6158866A (ja) * 1984-08-30 1986-03-26 三菱マテリアル株式会社 高融点金属珪化物基複合材料の製造法
JPS61294816A (ja) * 1985-06-21 1986-12-25 Matsushita Electronics Corp 半導体装置の製造方法
US4751198A (en) * 1985-09-11 1988-06-14 Texas Instruments Incorporated Process for making contacts and interconnections using direct-reacted silicide
US4818723A (en) * 1985-11-27 1989-04-04 Advanced Micro Devices, Inc. Silicide contact plug formation technique
JPS62213277A (ja) * 1986-03-14 1987-09-19 Nec Corp 半導体装置の製造方法
JPS63116A (ja) * 1986-06-19 1988-01-05 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6377117A (ja) * 1986-09-19 1988-04-07 Fujitsu Ltd 半導体装置の製造方法
JPS63120419A (ja) * 1986-11-10 1988-05-24 Matsushita Electronics Corp 半導体装置の製造方法
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
JP2776826B2 (ja) * 1988-04-15 1998-07-16 株式会社日立製作所 半導体装置およびその製造方法
JPH06276518A (ja) * 1993-03-22 1994-09-30 Sony Corp 画像処理装置
JPH06321829A (ja) * 1993-05-07 1994-11-22 Taiho Yakuhin Kogyo Kk α，α−ジメチルシクロヘキサンカルビノール誘導体又はその塩

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0128304A1 (en) * 1983-05-06 1984-12-19 Texas Instruments Incorporated Method of forming a metallic silicide
EP0211318A1 (de) * 1985-07-29 1987-02-25 Siemens Aktiengesellschaft Verfahren zum selektiven Auffüllen von in Isolationsschichten geätzten Kontaktlöchern mit metallisch leitenden Materialien bei der Herstellung von höchstintegrierten Halbleiterschaltungen sowie eine Vorrichtung zur Durchführung des Verfahrens
EP0248445A2 (en) * 1986-06-06 1987-12-09 Hitachi, Ltd. Semiconductor device having a diffusion barrier and process for its production
EP0286182A1 (en) * 1987-04-08 1988-10-12 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising a titanium disilicide layer

Also Published As

Publication number Publication date
JP2528961B2 (ja) 1996-08-28
JPH02194524A (ja) 1990-08-01
FR2641126A1 (en) 1990-06-29
KR900010993A (ko) 1990-07-11
KR930004295B1 (ko) 1993-05-22
US5070038A (en) 1991-12-03
FR2641126B1 (enExample) 1992-11-27
GB2226446A (en) 1990-06-27
DE3908676A1 (de) 1990-06-28
GB8921421D0 (en) 1989-11-08

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20090921