GB2165991A - Merged nonvolatile memory cell with floating gate superimposed on the control and selection gate - Google Patents
Merged nonvolatile memory cell with floating gate superimposed on the control and selection gate Download PDFInfo
- Publication number
- GB2165991A GB2165991A GB08524040A GB8524040A GB2165991A GB 2165991 A GB2165991 A GB 2165991A GB 08524040 A GB08524040 A GB 08524040A GB 8524040 A GB8524040 A GB 8524040A GB 2165991 A GB2165991 A GB 2165991A
- Authority
- GB
- United Kingdom
- Prior art keywords
- superimposed
- gate
- floating gate
- control
- merged
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 3
- 238000010168 coupling process Methods 0.000 abstract description 3
- 238000005859 coupling reaction Methods 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 8
- 239000004020 conductor Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000006399 behavior Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- FIPWRIJSWJWJAI-UHFFFAOYSA-N Butyl carbitol 6-propylpiperonyl ether Chemical compound C1=C(CCC)C(COCCOCCOCCCC)=CC2=C1OCO2 FIPWRIJSWJWJAI-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
A modified merged coil has the floating gate (5) superimposed on the control and selection gate (9), made in a single piece. Between the two gates is interposed a dielectric (12) formed of silicon oxide or alternatively a silicon oxide (12') and silicon nitride (12'') coupling. <IMAGE>
Description
SPECIFICATION
Merged nonvolatile memory cell with floating gate superimposed on the control and selection gate
The present invention relates to a merged nonvolatile memory cell with floating gate superimposed on the control and selection gate.
A merged cell is known to be a floating gate nonvolatile memory cell in which the control gate and the selection gate are formed in a single piece having the control part superimposed on the floating gate which is in turn superimposed on a monocrystalline silicon substrate with doped drain and source areas and an interposed channel area and the selection part superimposed on the source area of the silicon substrate. Silicon oxide is present with dielectric functions.
In merged cells, as in general in all floating gate memory cells, it is important to ensure high charge conservation capacity, both positive and negative, in the floating gate. The most critical condition for the loss of charge through the dielectric between the floating gate and the control gate occurs in the cell in a nonconductive state, i.e. with a negatively charged floating gate, during the reading phase when the control gate is polarized positively. In this condition the two electrical fields in the dielectric generated by the stored negative charge and the positive polarization of the control gate are of the same sign and are added together. But if the cell is in the conductive state with the floating gate charged positively and in reading condition the two electrical fields are of opposite sign and give a lower resulting electrical field.
in accordance with the invention it has now been found that the above objective can be achieved through a modified merged cell characterized in that it has the floating gate superimposed on the control and selection gate.
In other words the merged cell in accordance with the invention provides an inverted gate arrangement as compared with the disposition of conventional merged cells.
This allows use of the intrinsic characteristic of the oxide interposed between the two gates which consists of being a poor conductor when the upper gate is polarized negatively with respect to the lower one but a better conductor in the opposite situation.
It is clear that in the cell according to the invention, the floating gate being on top, the assymetry of the dielectric conduction characteristic is utilized, i.e. in the condition wherein the electrical field has the higher modulus value it is in the direction in which the dielectric has the lowest conduction while with conventional cells the opposite takes place.
The effect is increasted if, in accordance with a preferred embodiment of the present invention the dielectric placed between the two gates is not only oxide but oxide with superimposed silicon nitride. Tests showed that such a coupling increases the diversity of behaviour in both conduction directions.
The final result of all this is that for a given functional efficiency it is possible to make a cell with a thinner dielectric and hence reduced overall dimensions.
The features of the present invention will be better understood by observing the drawings wherein:
Figure 1 shows the structural configuration of a merged cell in accordance with the invention;
Figure 2 shows a diagram representing the manner of operation of the cell of Fig. 1; and
Figure 3 shows an oxide-nitride coupling which may be used as a dielectric between the two gates of the cell of Fig. 1.
With reference to Fig. 1, a merged cell is seen having a monocrystalline silicon substrate 1 provided with a doped drain area 2 and a doped source area 3 with an interposed channel area 4.
A floating polycrystalline silicon gate 5 is superimposed on the substrate 1 with a part 6 having a portion 7 near the drain area 2 and another part 8 superimposed on the control and selection gate 9 next to the source area 3.
Silicon oxide 10 surrounds the two gates 5 and 9, defining a thin oxide area 11 uner the portion 7 of the floating gate and a dielectric layer 12 between the two superimposed gates.
The intrinsic characteristics of the oxide cause differing behaviour of the cell depending on the polarization state of the floating gate. If the floating gate has a more positive potential than the control gate the oxide becomes a conductor with a relatively lower nominal electrical field. But this is the condition in which it is difficult to generate a high electrical field. If contrariwise the floating gate has a more negative potential than the control gate the oxide becomes a conductor only with higher electrical fields. It is thus possible to design cells with thinner dielectric cells since they will bear a higher electrical field than there would be with the floating gate charged with electrons without causing losses of charge.
The two situations are illustrated by curves
A and B of Fig. 2, voltage V being given on the abscissas and current I on the ordinates.
The above behaviour is further increased if the dielectric 12 is made up not of mere oxide but of an oxide-nitride sandwich such as shown in Fig. 3 where the oxide is indicated with 12' and the nitride with 12".
The manufacturing proces for the cell makes it possible to grow a thick oxide between the monocrystalline silicon and the first layer of polycrystalline silicon and a thinner dielectric, ie oxide or oxide & nitride, between the monocrystalline silicon and the second layer of polycrystalline silicon.
The utility of having available these two dielectrics of different thickness so as to be able to make the high voltage circuitry thicker and thus have higher breakdown voltages and the low voltage circuitry with thinner oxide or with the oxide-nitride sandwich so as to secure faster circuits will be immediately clear to persons skilled in the art.
Claims (3)
1. Merged nonvolatile memory cell comprising a silicon substrate with doped drain and source areas, a floating gate, a control and selection gate in a single piece and a dielectric interposed between said gates, chracterized in that said floating gate is superimposed on said control and selection gate.
2. Memory cell in accordance with claim 1 characterized in that said dielectric is made up of silicon oxide.
3. Memory cell in accordance with claim 1, characterized in that said dielectric is made up of silicon oxide and silicon nitride superimposed to said oxide.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT8423282A IT1213229B (en) | 1984-10-23 | 1984-10-23 | MERGED NON-VOLATILE MEMORY CELL WITH FLOATING GATE OVERLAPPING THE CONTROL AND SELECTION GATE. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8524040D0 GB8524040D0 (en) | 1985-11-06 |
| GB2165991A true GB2165991A (en) | 1986-04-23 |
Family
ID=11205624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08524040A Withdrawn GB2165991A (en) | 1984-10-23 | 1985-09-30 | Merged nonvolatile memory cell with floating gate superimposed on the control and selection gate |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS61101079A (en) |
| DE (1) | DE3537037A1 (en) |
| FR (1) | FR2572211B1 (en) |
| GB (1) | GB2165991A (en) |
| IT (1) | IT1213229B (en) |
| NL (1) | NL8502732A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5057886A (en) * | 1988-12-21 | 1991-10-15 | Texas Instruments Incorporated | Non-volatile memory with improved coupling between gates |
| US6501123B2 (en) * | 2001-03-06 | 2002-12-31 | Macronix International Co., Ltd. | High gate coupling non-volatile memory structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4020007C2 (en) * | 1989-06-22 | 1994-09-29 | Nippon Telegraph & Telephone | Non-volatile memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0042964A1 (en) * | 1980-06-18 | 1982-01-06 | International Business Machines Corporation | Memory matrix using one-transistor floating gate MOS cells |
| GB2116367A (en) * | 1982-03-09 | 1983-09-21 | Rca Corp | An electrically alterable, nonvolatile floating gate memory device |
| GB2117177A (en) * | 1982-03-09 | 1983-10-05 | Rca Corp | An electrically alterable, nonvolatile floating gate memory device |
| GB2126788A (en) * | 1982-03-09 | 1984-03-28 | Rca Corp | An electrically alterable nonvolatile floating gate memory device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5263684A (en) * | 1975-11-20 | 1977-05-26 | Toshiba Corp | Non-volatile semiconductor memory device |
| CA1119299A (en) * | 1979-02-05 | 1982-03-02 | Abd-El-Fattah A. Ibrahim | Inverse floating gate semiconductor devices |
| JPS5776878A (en) * | 1980-10-31 | 1982-05-14 | Fujitsu Ltd | Semiconductor memory device |
| JPS59105371A (en) * | 1982-12-08 | 1984-06-18 | Hitachi Ltd | Non-volatile semiconductor device |
-
1984
- 1984-10-23 IT IT8423282A patent/IT1213229B/en active
-
1985
- 1985-09-30 GB GB08524040A patent/GB2165991A/en not_active Withdrawn
- 1985-10-07 NL NL8502732A patent/NL8502732A/en not_active Application Discontinuation
- 1985-10-17 DE DE19853537037 patent/DE3537037A1/en not_active Withdrawn
- 1985-10-22 JP JP60234660A patent/JPS61101079A/en active Pending
- 1985-10-23 FR FR858515759A patent/FR2572211B1/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0042964A1 (en) * | 1980-06-18 | 1982-01-06 | International Business Machines Corporation | Memory matrix using one-transistor floating gate MOS cells |
| GB2116367A (en) * | 1982-03-09 | 1983-09-21 | Rca Corp | An electrically alterable, nonvolatile floating gate memory device |
| GB2117177A (en) * | 1982-03-09 | 1983-10-05 | Rca Corp | An electrically alterable, nonvolatile floating gate memory device |
| GB2126788A (en) * | 1982-03-09 | 1984-03-28 | Rca Corp | An electrically alterable nonvolatile floating gate memory device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5057886A (en) * | 1988-12-21 | 1991-10-15 | Texas Instruments Incorporated | Non-volatile memory with improved coupling between gates |
| US6501123B2 (en) * | 2001-03-06 | 2002-12-31 | Macronix International Co., Ltd. | High gate coupling non-volatile memory structure |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2572211A1 (en) | 1986-04-25 |
| DE3537037A1 (en) | 1986-04-24 |
| FR2572211B1 (en) | 1991-09-13 |
| IT8423282A0 (en) | 1984-10-23 |
| NL8502732A (en) | 1986-05-16 |
| JPS61101079A (en) | 1986-05-19 |
| GB8524040D0 (en) | 1985-11-06 |
| IT1213229B (en) | 1989-12-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |