GB2116367A - An electrically alterable, nonvolatile floating gate memory device - Google Patents

Abstract

In a nonvolatile, floating gate memory structure the floating gate (24) is substantially shielded from the substrate (10) by the program or control gate (22). The program or control gate (22) has an aperture (40) located over an auxiliary channel region (20). A portion of the floating gate (24) extends through the aperture (40) to allow charge to be placed on the floating gate. The auxiliary channel region (20) may be connected via an extension (15) to the source region (Figs. 1 to 1C) or to a doped intermediate region (42) joining the memory and select channels (Figs. 2 to 2B). <IMAGE>

Description

SPECIFICATION An electrically alterable. nonvolatile floating gate memory device This invention relates, in general, to semiconductor memory devices and more particularly, to electrically alterable, nonvolatile floating gate memory devices.

The microprocessor-based systems, as well as the related arts, have long required electrically alterable read only memory (EAROM) elements that were nonvolatile, and many devices incorporating such elements have, to some extent, filled this need. However, as the computer arts have become more complex in nature and have required higher speeds and greater capacity, there now exists the need for a high-density memory device that may be easily programmed or "written" and, as the occasion arises, to reprogram ("erase" and "rewrite") the device in the field. To this end, devices are presently available to design engineers that exhibit nonvolatile characteristics but, as will be discussed, they have inherent shortcomings that are overcome by the subject invention.

One such device resides in the family of Floating Gate Avalanche Metal Oxide Semiconductor (FAMOS) devices. The advantage of this type of device resides in the fact that it is independent of any outside current to maintain the stored information in the event that power is lost or interrupted. Since this device is independent of any outside power, there is also no need to refresh the device, which feature results in a significant savings in power.

The floating gate family of devices usually has source and drain regions of a given conductivity type, formed in a substrate of the opposite conductivity type, at the surface thereof. Between the source and drain regions, and on the surface of the substrate, a gate structure is formed by first applying a thin insulating layer followed by a conductive layer (the floating gate) followed by a second insulating layer in order to completely surround the floating gate and insulate it from the remainder of the device. A second conductive layer (usually referred to as the control gate) is formed over the second insulating layer (in the region of the floating gate) to complete the gate structure. Such devices are exemplified in U.S. Letters Patent 3,500,142 which issued to D. Kahng on March 10, 1970 and U.S. Letters Patent 3,660,819 which issued to D.Frohman-Bentchkowsky on May 2, 1972.

The major drawback of these prior-art devices resides in the fact that high fields are required to produce the necessary avalanche breakdown in order for charge to be placed on the floating gate.

Further, to erase the charge appearing on the floating gate, the entire device must be provided with a transparent window so that it may be flooded with energy in the ultra violet or x-ray portion of the sprectrum. Thus, it is extremely difficult to erase a single "word" without erasing all the charge on the device, then requiring that the entire device be completely reprogrammed. Further, the erasing step required an extremely long period of exposure time, of the order of about 30 to 45 minutes, with the device or chip removed from the equipment.

In recent years, the art has progressed to the point where nonvolatile, floating gate read only memory devices have been produced which are electrically alterable. One such memory cell has been described in detail in an article entitled "16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage" by W. S. Johnson, et al., ELECTRONICS, February 28, 1980, pp. 113-117. In this article, the authors describe a "Floating-Gate Tunnel Oxide" structure wherein a cell using a polycrystalline silicon (polysilicon) floating gate structure is charged with electrons (or holes) through a thin oxide layer positioned between the polycrystalline silicon gate and the substrate. The Fowler-Nordheim tunneling mechanism is used to charge the polycrystalline silicon gate.An elevation view of a typical device is described and shown in Figure 1 of the article, wherein the floating gate member represents the first polycrystalline silicon level. By using this type of structure (a structure wherein the first-level polycrystalline silicon, which represents the floating gate and is closest to the substrate, is covered by a second polycrystalline silicon level), an excessively high floating gate-to-substrate capacitance is produced. A certain area of floating gate is necessary in order to maintain close coupling between the first polycrystalline silicon level and next deposited or second polycrystalline silicon level.It has been found that some manufacturers etch away portions of the first polysilicon level, in order to reduce the capacitance between the floating gate and the substrate, without substantially reducing the capacitance between the first and second polycrystalline silicon levels.

The nonvolatile memory cell of the present invention uses the Fowler-Nordheim Tunneling mechanism to charge the polycrystalline silicon floating gate. However, in the present invention, the polycrystalline silicon floating gate is a second level of polycrystalline silicon rather than the first level, in order to provide a structure wherein the second-level polycrystalline silicon (the floating gate) is shielded from the substrate by the first-level polycrystalline silicon.The program or control gate (firstlevel polycrystalline silicon) is provided with an aperture, and the second-level polycrystalline silicon (floating gate) is disposed thereover with a small portion of the second-level polycrystalline silicon floating gate extending through the aperture in the first-level polycrystalline silicon so that only a relatively small area of the second-level polycrystalline silicon is coupled to the substrate.

In the drawing: Figure 1 is a plan view of one embodiment of a memory device made in accordance with the teaching of the present invention; Figure 1A is a cross-sectional view of the device of Figure 1 taken along line 1 A~1 A of Figure 1; Figure 1 B is a cross-sectional view of the device of Figure 1 taken along line 1 B-1 B of Figure 1; Figure 1 C is a cross-sectional view of the device of Figure 1 taken along line 1 C--l C of Figure 1; Figure 2 is a plan view of another embodiment of a memory device made in accordance with the teaching of the present invention; Figure 2A is a cross-sectional view of the device of Figure 2 taken along line 2A-2A of Figure 2; and Figure 2B is a cross-sectional view of the device of Figure 2 taken along line 2B-2B of Figure 2.

Figures 1, 1 A, 1 B and 1 C show a substrate 10 having a line 13 consisting of active regions and including doped source and drain regions 14 and 16, an intervening doped region 42 and a channel region 18. At the surface of substrate 10 is formed a field oxide 12, which field oxide 12 defines the limits of the active regions which also include source extension 15 and auxiliary channel region 20 as well as line 13. Above field oxide 12 and channel regions 18 and 20 is a layer of insulating oxide 35, and on top of oxide layer 35 is the first-level polycrystalline silicon layer (program or control gate line) 22. As shown in Figures 1,1 A and 1 C, the first-level polycrystalline silicon layer 22 is a line extending in the same general direction as line 13 and is parallel thereto.However, for the sake of clarity, this first-level polycrystalline silicon (program or control) gate line 22 is shown in Figures 1,1 A and 1 B as being laterally separated from line 13. It will be understood that good design techniques dictate that first-level polycrystalline silicon (program or control) gate line 22 may be as close as coincident with line 13 in order to reduce the gate-to-substrate capacitance. Additionally, as shown in Figures 1,1 A and 1 C, the first-level polycrystalline silicon (program or control) gate line 22 is provided with an aperture or charging window 40.Source region 14 is shown in Figures 1 and 1A as being provided with a source extension 1 5 which extends laterally outwardly from source region 14 toward the area under first-level polycrystalline silicon (program or control) gate line 22 and an auxiliary channel portion 20, which is laterally aligned with extension 15 to extend under the aperture 40 formed in firstlevel polycrystalline silicon (program or control) gate line 22. It is understood that the source extension 15 is doped with the same type conductivity modifiers as source region 14, while auxiliary channel region 20, as shown in Figures 1 A and 1 C, is a channel region formed in substrate 10.

As shown in Figures 1, 1 A, 1 B and 1 C, a second-level polycrystalline silicon floating gate 24 is provided having a generally Z shaped configuration and having the major portion thereof positioned over the first-level polycrystalline silicon (program or control) gate line 22 and the remainder thereof formed over channel region 18 in line 13. The portion of floating gate 24 over aperture 40 extends down into the aperture and is separated from channel region 20 by a thickness of oxide which is thinner than the oxide layer which insulates the first-level polycrystalline silicon gate line 22 from substrate 10. Source and drain contact openings 32 and 34 are shown in direct communication with source and drain regions 14 and 16, respectively.Source line 26 makes contact to source region 14 through contact opening 32, while drain line 28 makes contact to drain 16 through contact opening 34. As shown in Figures IA, B and 1 C, drain and source lines 26 and 28 are insulated from the first and second polycrystalline silicon layers 22 and 24 by means of insulating layer 38. In addition, at the same time that second-level polycrystalline silicon floating gate layer 24 is formed, there is also formed a a select gate (word line) 30, which is at the same level as floating gate 24 being insulated from firstlevel polycrystalline silicon, layer 22 by oxide layer 36, and extends over a channel region between doped regions 16 and 16' in line 13.

As shown in Figures 1 and 1 A, the source extension 15 is doped with the same type conductivity modifiers and is formed at the same time that source region 14 is formed. Additionally, it should be noted, that the oxide thickness beneath the second-level layer 24 at aperture 40 (Figures 1 A and 1 C) is about 90-120 Angstroms. The thickness of the gate oxide appearing between the first-level polycrystalline silicon layer 22 and the substrate 10 is of the order of about 1000 Angstroms, while the thickness of the oxide layer 36 covering the first-level polycrystalline silicon layer 22 is of the order of about 2500 Angstroms.

As shown in Figures 1 A, 1 B and 1 C, the second-level polycrystalline floating gate 24 will be deposited within the aperture formed by window 40 and, when it is defined by masking and etching, it is made to extend over the line 13 which will be subsequently defined as the source region 14, channel region 18, and drain region 16. It should be noted that anyone skilled in the art will recognize that in order to achieve an aligned gate device, the doping of source 14 and drain 16 should be accomplished after the gates have been formed. At the time that second-level polycrystalline silicon floating gate 24 is formed, the select gate (word line) 30 is also formed. This was done during the masking and etching of the first-level polycrystalline silicon layer 22 in a well known manner to simultaneously form both floating gate 24 and select gate (word line) 30. Thereafter, the device is provided with another oxide layer 38 (Figures 1 A, 1 B and 1 C) of the order about 6000 Angstroms, in order to provide the insulation for the subsequent formation of drain and source lines 26 and 28.

After the formation of oxide layer 38, the surface of the device is appropriately masked and etched to form contact openings 32 and 34 (Figures 1 and 1 A) which communicate with source region 14 and drain region 16, respectively. Thereafter, a layer of e.g. aluminum can be deposited, masked and etched to form lines 26 and 28 which represent the source line and drain line, respectively. As shown in Figures 1 A, 1 B and 1 C, field oxide 12 has been grown to insure isolation around this structure and similar adjacent structures.

With reference again to Figures 1, 1 A, 1 B and 1 C, it should be observed now that, to obtain optimum tunneling, it is important to maintain as much of the applied field as possible between the floating gate and substrate. Accordingly, the floating gate (24) -to- substrate (18) capacitance, as well as the floating gate (24) -to- auxiliary channel portion (20) capacitance, must be reduced while the program or control gate (22)-to-floating gate (24) capacitance must be increased to as large a value as possible. However, the floating gate (24) -to- channel extension (20) capacitance is governed by the thickness of the oxide layer under the floating gate 24 at the window 40.This oxide thickness should not be incrased much above a thickness of about 90-120 Angstroms, as this would tend to decrease current density which would then require higher fields or longer times to charge the device.

As previously stated, a premise of the present invention resides in the reversal of the positions of the program (control) gate 22 (now the first-level polycrystalline silicon layer) and the floating gate 24 (now the second-layer polycrystalline silicon layer). Thus, the second-level polycrystalline silicon layer (floating gate) 24 -to- substrate 10 capacitance is greatly reduced. In fact, this capacitance has been reduced to the point where it is almost negligible due to the presence of the intervening first-level polycrystalline silicon layer 22 under the second-level polycrystalline silicon floating gate 24 except for the two critical areas, namely: that portion of floating gate 22 that couples to channel extension 20 through aperture 40 (the charging portion) and that portion of floating gate 22 that couples to channel 18.This latter portion, when charged, determines the threshold level of the device (the thresholddetermining portion). The charge-mode capacitance is represented by that portion of floating gate 24 that extends through aperture 40.

Another feature of the present invention resides in the fact that a metal or a third-level polycrystalline silicon bus 26 may now be used to add to the coupling between the source line and the floating gate 24, since the second-level polycrystalline silicon gate 24 is now positioned to be easily coupled to bus 26. This is a feature which could not be achieved in the prior art.

The following table shows the potentials which are applied to the various elements of the device, herein shown, in order to erase, program or write, and read the device. In the table, the various potentials shown under the columns entitled "ERASE", "WRITE" and "READ" are applied to the elements shown under the column entitled "ELEMENT'.

ELEMENT ERASE WRITE READ Drain (34) +20 Volts O Volts +5 Volts Source (32) +20 Volts O Volts O Volts Program line (22) 0 Volts +20 Volts +5 Volts Substrate (10) 0 Volts O Volts O Volts Word line (30) +20 Volts +20 Volts +5 Volts Thus, as shown in the above table, the device is erased by placing a 20 volt signal on drain 34, source 32, and word line 22 of Figure 1. This erase cycle will place a positive charge on floating gate 24 which puts channel region 18 in a low-threshold (high-conduction) state. However, there will be no electron conduction through channel region 18 unless the proper "read" voltages, as indicated in the above table, are applied. This provides a convenient method of checking the devices to determine that all elements in an array are, in fact, erased.To "write", a 20 volt signal is placed on program line 22 and on word line 30 which, in effect, now places a negative charge on floating gate 24, which now puts channel region 18 in a high-threshold (low-conduction) state. Under these conditions, the negative charge on the floating gate 24 will prevent channel 18 from being inverted and, thus, no conduction can take place between source 32 and drain 34 during the read cycle. To read the device, that is, to determine whether the cell is in a high-threshold or a low-threshold state, 5 volts are placed on the drain 34, program line 22 and word line 30. The indication of conduction will thus signify the presence of a low-threshold-state (high-conduction-state) device.

Referring now to Figures 2, 2A and 2B there is shown another embodiment of the present invention which develops from the embodiment of the prior figures. It will be seen that similar elements in Figures 1 and 2 will be similarly numbered. The device shown in Figure 2 differs from the device shown in Figure 1 by omitting extension 15, at source 14 and instead providing doped region 42 between source 14 and drain 16 with a doped extension 43. Independent channel region 44 lies beneath the select gate (word line) 30. The doped extension 43 extends in a direction toward first-level polycrystalline silicon layer 22 in the same manner as described with regard to Figure 1. However, in this latter embodiment, auxiliary channel region 20 is now provided to be extended from doped extension 43, and aperture 40 is provided over channel region 20.In this embodiment, the line 13 containing the source region 14 and drain region 16, as shown in Figure 2A, has both channel region 18, and most of doped region 42 appearing where only channel region 18 occurred in Figure 1.

Figure 2B shows the relationship of floating gate 24 to channel region 20 and window 40. In all other respects, the devices of Figures 1 and of Figure 2 will function in much the same manner, and will be erased, written and read as set forth in the above table.

The following process sequence is one example of the manner in which the present device may be fabricated: 1. Define active regions including line 13, extension 15 and auxiliary channel region 20 (Figure 1).

In Figure 2, this includes line 13, doped region 42, doped extension 43 and auxiliary channel region 20); 2. Implant or diffuse N- type dopant into auxiliary channel region 20; 3. Grow oxide layer 35 to a thickness of about 1000 Angstroms; 4. Deposit first-level polycrystalline silicon layer 22; 5. Mask and etch first polycrystalline silicon layer 22 including aperture 40; 6. Remove mask and grow oxide layer 36 to a thickness of about 2500 Angstroms (this oxide is deposited over the channel region 1 8 and in aperture 40); 7. Mask layer 36 with layer of photoresist in all areas except aperture 40 and etch the oxide in the aperture 40; 8. Remove mask and grow thin oxide in aperture 40 to thickness of about 90-120 Angstroms over auxiliary channel region 20; 9. Deposit second-level polycrystalline silicon layer; 10.Mask and etch second polycrystalline silicon layer to form floating gate 24 and select gate (word line) 30; and 11. Standard processing procedures continue from this point and include the N+ diffusions for source and drain regions 14 and 16, extension 15, independent doped region 42 and doped extension 43 (Figure 2), formation of oxide layer 38 and the formation of contact openings 32 and 34 followed by metallization to form lines 26 and 28, etc.

In Figures 1 and 2, a single-cell floating gate memory device is described; for this device to have maximum utility, more than a single memory cell is required. Accordingly, it should now be obvious to those skilled in the art that a plurality of these devices may be arranged in rows and columns to form an array, wherein various cells in the array may be selected and electrically programmed and read in accordance with the description previously given with regard to Figures 1 and 2.

Claims (7)

Claims

1. A floating-gate memory device including semi-conductor material having a channel region of a first conductivity type material defined therein between spaced apart first and second doped regions of a second conductivity type formed in the semiconductor material at the surface thereof, said channel region being supportive of current flow between the doped regions; an extended portion disposed next to one of the doped regions and comprising a first section of said second conductivity type adjoining the doped region and a second section of said first conductivity type adjoining the first section; a first layer of polycrystalline silicon insulated from the semiconductor material and forming a line positioned over the second section of the extended portion and adjacent to the doped regions and channel region;; a charging window in the first layer of polycrystalline silicon aligned with the second section of the extended portion; and a second layer of polycrystalline silicon extending over and insulated from both a portion of the first layer of polycrystalline silicon and the channel region, and extending through the charging window for coupling to the second section of the extended portion.

2. A memory device according to Claim 1 wherein the first and second doped regions constitute source and drain regions, respectively; and said extended portion adjoins the source region.

3. A memory device according to Claim 1 further comprising: a third doped region; and a second channel region separating the second and third doped regions.

4. A memory device according to Claim 3 wherein the first and third doped regions are source and drain regions respectively, the second doped region is positioned between these channel and drain regions, and said extended portion adjoins to the second doped region.

5. A memory device according to Claim 2 or Claim 4 wherein the first layer of polycrystalline silicon, a program/control gate and the second layer of polycrystalline silicon constitutes a floating gate.

6. A memory device according to Claim 5 further comprising a word line positioned adjacent the floating gate and lying over and insulated from the channel region, or the second channel region (as the case may be), whereby when a voltage of a first value is applied to the drain region, the source region and the word line and 0 (zero) volts is applied to both the semiconductor material and the program/ control gate, the memory device is erased to a low-threshold, high-conduction state, whereas when 0 (zero) volts is applied to the drain region, the source region and the substrate and a voltage of the first value is applied to the word line and program/control gate, the memory device is written to a highthreshold, low-conduction state.

7. A floating-gate memory device substantially as hereinbefore described with reference to Figure 1 or Figure 2 of the accompanying drawing.