CA1119299A - Inverse floating gate semiconductor devices - Google Patents
Inverse floating gate semiconductor devicesInfo
- Publication number
- CA1119299A CA1119299A CA000320834A CA320834A CA1119299A CA 1119299 A CA1119299 A CA 1119299A CA 000320834 A CA000320834 A CA 000320834A CA 320834 A CA320834 A CA 320834A CA 1119299 A CA1119299 A CA 1119299A
- Authority
- CA
- Canada
- Prior art keywords
- gate
- floating gate
- channel region
- selection gate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007667 floating Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000003874 inverse correlation nuclear magnetic resonance spectroscopy Methods 0.000 abstract 1
- 239000007943 implant Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 206010022998 Irritability Diseases 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003389 potentiating effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Non-Volatile Memory (AREA)
Abstract
INVERSE FLOATING GATE SEMICONDUCTOR DEVICES
Abstract of the Disclosure An MOS stacked gate structure for an EPROM has an upper floating gate and a lower selection gate permitting shorter erasal time, lower selection gate voltage and a compact EPROM structure.
- i -
Abstract of the Disclosure An MOS stacked gate structure for an EPROM has an upper floating gate and a lower selection gate permitting shorter erasal time, lower selection gate voltage and a compact EPROM structure.
- i -
Description
~il9Z99 The Erasable Programmable Read Only Memory (EPROM) is being used extensively in modern digital systems.
The present invention proposes an alternative EPROM cell structure adapted to be integrated into a large EPROM array for better overall performance.
In p-channel MOS technology, EPROM's have been designed and fabricated using a FAMOS (floating gate avalanche metal-oxide-semiconductor) type device which relies on the avalanche breakdown of a junction to produce electron-hole pairs, the electrons being injected into a floating or insulated gate immediately above the avalanched junction. These injected electrons serve to modify the surface conductance of the semiconductor under the gate region, to program the previously non-conducting device into a conductive mode. The programming voltage of this type of device is usually greater than 45 volts. In n-channel MOS technology, EPROM's incorporating stacked gate structures are known which do not require high programming voltages. In these structures, two levels of gate conductors are required: one, the floating gate, provides the programming function and the other the selection gate, located above the floating gate, provides the cell selection function.
The present invention is superficially similar to these prior stacked gate structures. However, it differs fundamentally in that the roles of the two levels of gate conductors are reversed. Thus, the invention proposes using the upper gate as a floating gate to store injected charge, while the lower gate is used as a selection gate. The invention offers several advantages over the known stacked gate construction, thus:
(i) shorter erasal time when exposed to ultraviolet radiation;
_ 1 lll9Z99 (ii) better coupling between selection gate and floating gate, whereby a lower selection gate voltage may be used during programming;
(iii) the threshold voltage of the unprogrammed device is mainly controlled by the selection gate to source and selection gate to substrate voltages. The selection gate conductor material can be used to form the gates of any other MOS
transistors to provide a uniform threshold voltage for all devices;
(iv) achievement of a more compact cell structure by using the selection gate as a mask for automatically locating a subsequent diffusion.
An embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which:-Figure 1 shows a sectional view of an inverted stacked gate MOS device according to the invention;
Figure 2 shows, schematically, the device ofFigure 1 in its circuit configuration; and Figure 3 shows a schematic plan view of an EPROM.
Fabrication The inverted stacked gate injection MOS device 1 of Figure 1 is fabricated using conventional MOS fabrication techniques; see, for example, H. Iizuka, et al., "Stacked-~ate-Avalanche-Injection Type MOS (SAMOS) Memory," in Proc. 4th Conf.
Solid State Devices (Tokyo, Japan, Aug. 1972); also ibid., vol.
42, pp. 158-166, 1973j H. Iizuka, F. Masuoka, T. Sato, and l~l9Z99 M. Ishikawa, "Electrically Alterable Avalanche-Injection Type MOS
Read Only Memory With Stacked-Gate Structure", IEEE Trans.
Electron Devices, vol. ED-23, pp.379-387, 1976? B. Rossler and R.G. Miller, "Erasable And Electrically Reprogramable Read-Only Memory Using The N-Channel SIMOS One Transistor Cell", Siemens Forsch-u. Entwirkl-Ber., vol. 4, pp. 345-351, 1975.
An insulating oxide layer 2 and a polysilicon layer 3 are formed on a p-type silicon substrate, the layers being etched to the cross-sectional shape shown. A p+ type region 4 is then implanted or diffused in the substrate using the layers 2 and 3 to locate the implant. A second layer of polysilicon 5 on oxide 6 is then formed over the layer 3 and the implant 4. Finally, n+
type regions 7 and 8 are implanted or diffused into the substrate using the layers 2, 3, 5 and 6 to locate the implant or diffusion.
Operation In normal operation, the inverted stacked gate MOS
device functions as a MOS transistor. Referring to Figures 1 and
The present invention proposes an alternative EPROM cell structure adapted to be integrated into a large EPROM array for better overall performance.
In p-channel MOS technology, EPROM's have been designed and fabricated using a FAMOS (floating gate avalanche metal-oxide-semiconductor) type device which relies on the avalanche breakdown of a junction to produce electron-hole pairs, the electrons being injected into a floating or insulated gate immediately above the avalanched junction. These injected electrons serve to modify the surface conductance of the semiconductor under the gate region, to program the previously non-conducting device into a conductive mode. The programming voltage of this type of device is usually greater than 45 volts. In n-channel MOS technology, EPROM's incorporating stacked gate structures are known which do not require high programming voltages. In these structures, two levels of gate conductors are required: one, the floating gate, provides the programming function and the other the selection gate, located above the floating gate, provides the cell selection function.
The present invention is superficially similar to these prior stacked gate structures. However, it differs fundamentally in that the roles of the two levels of gate conductors are reversed. Thus, the invention proposes using the upper gate as a floating gate to store injected charge, while the lower gate is used as a selection gate. The invention offers several advantages over the known stacked gate construction, thus:
(i) shorter erasal time when exposed to ultraviolet radiation;
_ 1 lll9Z99 (ii) better coupling between selection gate and floating gate, whereby a lower selection gate voltage may be used during programming;
(iii) the threshold voltage of the unprogrammed device is mainly controlled by the selection gate to source and selection gate to substrate voltages. The selection gate conductor material can be used to form the gates of any other MOS
transistors to provide a uniform threshold voltage for all devices;
(iv) achievement of a more compact cell structure by using the selection gate as a mask for automatically locating a subsequent diffusion.
An embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which:-Figure 1 shows a sectional view of an inverted stacked gate MOS device according to the invention;
Figure 2 shows, schematically, the device ofFigure 1 in its circuit configuration; and Figure 3 shows a schematic plan view of an EPROM.
Fabrication The inverted stacked gate injection MOS device 1 of Figure 1 is fabricated using conventional MOS fabrication techniques; see, for example, H. Iizuka, et al., "Stacked-~ate-Avalanche-Injection Type MOS (SAMOS) Memory," in Proc. 4th Conf.
Solid State Devices (Tokyo, Japan, Aug. 1972); also ibid., vol.
42, pp. 158-166, 1973j H. Iizuka, F. Masuoka, T. Sato, and l~l9Z99 M. Ishikawa, "Electrically Alterable Avalanche-Injection Type MOS
Read Only Memory With Stacked-Gate Structure", IEEE Trans.
Electron Devices, vol. ED-23, pp.379-387, 1976? B. Rossler and R.G. Miller, "Erasable And Electrically Reprogramable Read-Only Memory Using The N-Channel SIMOS One Transistor Cell", Siemens Forsch-u. Entwirkl-Ber., vol. 4, pp. 345-351, 1975.
An insulating oxide layer 2 and a polysilicon layer 3 are formed on a p-type silicon substrate, the layers being etched to the cross-sectional shape shown. A p+ type region 4 is then implanted or diffused in the substrate using the layers 2 and 3 to locate the implant. A second layer of polysilicon 5 on oxide 6 is then formed over the layer 3 and the implant 4. Finally, n+
type regions 7 and 8 are implanted or diffused into the substrate using the layers 2, 3, 5 and 6 to locate the implant or diffusion.
Operation In normal operation, the inverted stacked gate MOS
device functions as a MOS transistor. Referring to Figures 1 and
2, the regions 7 and 8 function as the transistor source 9 and drain 11, and conducting layer 3 functions as the transistor gate. The gate is termed the selection gate 10 to distinguish it from a floating gate 12 which is the completely insulated polysilicon layer 5. The substrate channel region is represented at 13 in Figure 2.
Normal transistor action occurs when an appropriate potential difference exists between the drain 11 and the source 9 and a voltage exceeding a threshold level is applied to the selection gate 10. The threshold voltage is ~nfluenced.predominantly by charge stsred at the floating gate 12, the threshold, ;n the absence of stored charge being about 2 to 12V.
To program the device, i.e. to substantially raise ~19Z99 the threshold level, the selection gate is raised to about double the normal operating voltage and a voltage pulse is applied to the source. Electrons are accelerated towards the drain 11 by the potent;al difference between source and drain. The p+ implant 4 enhances the accelerating electric fleld near the drain 11 where the channel is covered by the floating gate, some of the electrons gaining sufficient energy to be injected across the oxide layer 6 into the floating gate 12 under the influence of an electric field across the oxide layer 6 owing to capacitive coupling between the selection and floating gates lO,and 12.
A lower selection gate programming voltage is required by the inverted stacked gate device than is the case with the conventional stacked gate device of equivalent size owing to more effic;ent capacitive coupling between the selection gate 10 and the floating gate 12. This is achieved because the floating gate/substrate capacitance can be made lower (thereby producing high floating gate/substrate voltage), without reducing the size of the floating gate; reduction in floating gate size would cause a consequent and undesirable reduction in the capacitive coupling between the gates.
As a result of the charge injection, the device threshold voltage is increased. When sufficient charge is stored in the floating gate, the threshold level of the device is so high that the device remains non-conducting even when a normal selection voltage is applied. Since there is no electrical connection to the floating gate, the injected charge can be stored for as long as a few decades, the device then being in its programmed mode.
Inverted stacked gate devices can, in practice, be made more compact than known stacked gate devices. Thus whereas conventional and inverted stacked gate devices both require an ~1~;Z~9 implant or diffusion under the floating gate, the polysilicon on oxide selection gate layer 2, 3 of the present invention provides a mask ensuring automatic and exact alignment of the implant or d;ffusion whereas in the prior art device, since the selection gate overlies the float;ng gate, the substrate implant must be formed without reference to either of the gates and is consequently somewhat oversized in order to allow some tolerance in positioning of the gates.
The stored charge on the floating gates of the inverted stacked gate device can be removed or "erased" by exposing the device to ultraviolet radiation. The erasure time is less than the known stacked gate device owing to the greater exposed area of the floating gate 12.
The inverted stacked gate device can be fabricated as a p-channel device with appropriate reversal of dopant polarities.
Since the oxide layer 6 tends to trap holes to a much greater extent than it does electrons, the n-channel embodiment is preferred.
The programming and erasing properties make the structure suitable for use in an integrated circuit array such as an EPROM. A schematic plan view of part of an EPROM is shown in Figure 3 which shows selection gates 15, floating gates 16, regions 17 over which insulating oxide extends, active regions 18 between the oxide regions 17, and aluminum leads 19 with contacts 20 to the n+ drain regions. The cells are usually located in an M x N matrix with all the N selection gates of the same columns connected to the word line and all the M drains of the same row connected to the bit line. The N word lines are connected to a one-of-N decoder and the M bit lines to a one-of-M decoder (not shown).
Normal transistor action occurs when an appropriate potential difference exists between the drain 11 and the source 9 and a voltage exceeding a threshold level is applied to the selection gate 10. The threshold voltage is ~nfluenced.predominantly by charge stsred at the floating gate 12, the threshold, ;n the absence of stored charge being about 2 to 12V.
To program the device, i.e. to substantially raise ~19Z99 the threshold level, the selection gate is raised to about double the normal operating voltage and a voltage pulse is applied to the source. Electrons are accelerated towards the drain 11 by the potent;al difference between source and drain. The p+ implant 4 enhances the accelerating electric fleld near the drain 11 where the channel is covered by the floating gate, some of the electrons gaining sufficient energy to be injected across the oxide layer 6 into the floating gate 12 under the influence of an electric field across the oxide layer 6 owing to capacitive coupling between the selection and floating gates lO,and 12.
A lower selection gate programming voltage is required by the inverted stacked gate device than is the case with the conventional stacked gate device of equivalent size owing to more effic;ent capacitive coupling between the selection gate 10 and the floating gate 12. This is achieved because the floating gate/substrate capacitance can be made lower (thereby producing high floating gate/substrate voltage), without reducing the size of the floating gate; reduction in floating gate size would cause a consequent and undesirable reduction in the capacitive coupling between the gates.
As a result of the charge injection, the device threshold voltage is increased. When sufficient charge is stored in the floating gate, the threshold level of the device is so high that the device remains non-conducting even when a normal selection voltage is applied. Since there is no electrical connection to the floating gate, the injected charge can be stored for as long as a few decades, the device then being in its programmed mode.
Inverted stacked gate devices can, in practice, be made more compact than known stacked gate devices. Thus whereas conventional and inverted stacked gate devices both require an ~1~;Z~9 implant or diffusion under the floating gate, the polysilicon on oxide selection gate layer 2, 3 of the present invention provides a mask ensuring automatic and exact alignment of the implant or d;ffusion whereas in the prior art device, since the selection gate overlies the float;ng gate, the substrate implant must be formed without reference to either of the gates and is consequently somewhat oversized in order to allow some tolerance in positioning of the gates.
The stored charge on the floating gates of the inverted stacked gate device can be removed or "erased" by exposing the device to ultraviolet radiation. The erasure time is less than the known stacked gate device owing to the greater exposed area of the floating gate 12.
The inverted stacked gate device can be fabricated as a p-channel device with appropriate reversal of dopant polarities.
Since the oxide layer 6 tends to trap holes to a much greater extent than it does electrons, the n-channel embodiment is preferred.
The programming and erasing properties make the structure suitable for use in an integrated circuit array such as an EPROM. A schematic plan view of part of an EPROM is shown in Figure 3 which shows selection gates 15, floating gates 16, regions 17 over which insulating oxide extends, active regions 18 between the oxide regions 17, and aluminum leads 19 with contacts 20 to the n+ drain regions. The cells are usually located in an M x N matrix with all the N selection gates of the same columns connected to the word line and all the M drains of the same row connected to the bit line. The N word lines are connected to a one-of-N decoder and the M bit lines to a one-of-M decoder (not shown).
Claims (5)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A field effect device comprising a p-type substrate, n-type source and drain regions formed in the substrate, a channel region extending between the source and the drain, a selection gate and floating gate stacked above said channel region, said gates being electrically insulated from one another and from the channel region by oxide layers, the floating gate having a first part overlying the selection gate and a second part projecting laterally beyond the selection gate extending closer to the channel region than the first part, and a heavily doped p-type region within the channel region and underlying said second part of the floating gate, said heavily doped p-type region acting, in operation of the device, to accelerate electrons along the channel region, the heavily doped p-type region vertically defined at one edge by the drain.
2. A field effect device as claimed in claim 1, in which the device is fabricated on a silicon substrate and has polysilicon gates.
3. An erasable programmable read-only memory having a plurality of devices as claimed in claim 1, having a matrix of leads for selecting individual devices.
4. In a method of making the device of claim 1, including the steps of forming the selection gate preparatory to forming the floating gate, an intermediate ion implantation step, using said selection gate as a mask to form the heavily doped p-type region within the channel region immediately laterally adjacent to the selection gate.
5. A method as claimed in claim 4, in which the floating gate forms part of a mask for implanting the source and drain into the substrate, whereby the channel region is confined to a region directly beneath the floating gate and the heavily doped p-type region is located in vertical alignment with the second part of the floaring gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000320834A CA1119299A (en) | 1979-02-05 | 1979-02-05 | Inverse floating gate semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000320834A CA1119299A (en) | 1979-02-05 | 1979-02-05 | Inverse floating gate semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1119299A true CA1119299A (en) | 1982-03-02 |
Family
ID=4113457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000320834A Expired CA1119299A (en) | 1979-02-05 | 1979-02-05 | Inverse floating gate semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1119299A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2523355A1 (en) * | 1982-03-09 | 1983-09-16 | Rca Corp | ELECTRICALLY MODIFIABLE FLOATING DOOR MEMORY WITH FLOATING DOOR |
| EP0162737A1 (en) * | 1984-04-06 | 1985-11-27 | STMicroelectronics S.A. | Electrically erasable and reprogrammable memory point comprising a floating gate above a control gate |
| FR2572211A1 (en) * | 1984-10-23 | 1986-04-25 | Sgs Microelettronica Spa | PERMANENT MEMORY CELL OF THE "MERGED" TYPE (FUSIONED) WITH A FLOATING GRID SUPERMITTED TO THE CONTROL AND SELECTION GRID |
| US5045488A (en) * | 1990-01-22 | 1991-09-03 | Silicon Storage Technology, Inc. | Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device |
| US5486480A (en) * | 1991-05-15 | 1996-01-23 | North American Philips Corporation | Method of fabrication of protected programmable transistor with reduced parasitic capacitances |
-
1979
- 1979-02-05 CA CA000320834A patent/CA1119299A/en not_active Expired
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2523355A1 (en) * | 1982-03-09 | 1983-09-16 | Rca Corp | ELECTRICALLY MODIFIABLE FLOATING DOOR MEMORY WITH FLOATING DOOR |
| EP0162737A1 (en) * | 1984-04-06 | 1985-11-27 | STMicroelectronics S.A. | Electrically erasable and reprogrammable memory point comprising a floating gate above a control gate |
| FR2572211A1 (en) * | 1984-10-23 | 1986-04-25 | Sgs Microelettronica Spa | PERMANENT MEMORY CELL OF THE "MERGED" TYPE (FUSIONED) WITH A FLOATING GRID SUPERMITTED TO THE CONTROL AND SELECTION GRID |
| US5045488A (en) * | 1990-01-22 | 1991-09-03 | Silicon Storage Technology, Inc. | Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device |
| US5486480A (en) * | 1991-05-15 | 1996-01-23 | North American Philips Corporation | Method of fabrication of protected programmable transistor with reduced parasitic capacitances |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4780424A (en) | Process for fabricating electrically alterable floating gate memory devices | |
| US5300802A (en) | Semiconductor integrated circuit device having single-element type non-volatile memory elements | |
| US3984822A (en) | Double polycrystalline silicon gate memory device | |
| US4122544A (en) | Electrically alterable floating gate semiconductor memory device with series enhancement transistor | |
| US5284785A (en) | Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and methods for making and using the same | |
| US6127696A (en) | High voltage MOS transistor for flash EEPROM applications having a uni-sided lightly doped drain | |
| US3996657A (en) | Double polycrystalline silicon gate memory device | |
| JP2555027B2 (en) | Semiconductor memory device | |
| US5444279A (en) | Floating gate memory device having discontinuous gate oxide thickness over the channel region | |
| US4112509A (en) | Electrically alterable floating gate semiconductor memory device | |
| EP0044384A2 (en) | Electrically alterable read only memory cell | |
| US4519849A (en) | Method of making EPROM cell with reduced programming voltage | |
| US4814286A (en) | EEPROM cell with integral select transistor | |
| EP0255489A2 (en) | Nonvolatile, semiconductor memory device | |
| EP0256993B1 (en) | Electrically alterable, nonvolatile, floating gate memory device | |
| US5411908A (en) | Flash EEPROM array with P-tank insulated from substrate by deep N-tank | |
| US5340760A (en) | Method of manufacturing EEPROM memory device | |
| KR100394425B1 (en) | A channel stop method for use in a thick field isolation region in a triple well structure | |
| KR100366599B1 (en) | High energy buried layer implant with flash providing low resistance pit-well to pyramid array | |
| US4486859A (en) | Electrically alterable read-only storage cell and method of operating same | |
| CA1119299A (en) | Inverse floating gate semiconductor devices | |
| US6268248B1 (en) | Method of fabricating a source line in flash memory having STI structures | |
| US5508955A (en) | Electronically erasable-programmable memory cell having buried bit line | |
| US5147816A (en) | Method of making nonvolatile memory array having cells with two tunelling windows | |
| US6611459B2 (en) | Non-volatile semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |