DE3537037A1 - FUSIONED NON-VOLATILE STORAGE CELL - Google Patents

Description

The invention relates to a fused non-volatile Memory cell according to the preamble of claim 1.

It is known that a fused cell is a non-volatile memory cell with potential floating gate in which the control gate and the select gate are integrally formed. It is the control part is arranged over the floating gate, which in turn is over a monocrystalline silicon substrate with doped drain and source zones and a channel zone located therebetween is arranged, and the selection part is arranged over the source region of the silicon substrate. It is silicon oxide with dielectric Functions available.

In the case of fused cells, it is the same as in general for all Floating gate memory cells important to have a high charge conservation capacity in the floating gate ensure for both positive and negative charge. The most critical condition for the loss of Charge through the dielectric between the floating gate and the control gate occurs in the cell in a non-conductive state, i.e. with a negatively charged floating gate, during the reading phase, if the control gate is positively biased. In this state, the two electric fields in the dielectric, which are generated due to the stored negative charge and the positive bias of the control gate, have the same sign and add up to each other. However, if the cell is floating with a positively charged Gate is in the conductive state and under the read condition, the two electrical fields are opposite Sign and result in a lower resulting electric field.

According to the invention it has now been recognized that the can achieve resulting goals with a modified fused cell, which is characterized by it is that its floating gate is located above the control and select gate.

In other words, the invention looks fused Cell has an inverted gate arrangement compared to the arrangement of conventional fused cells.

This makes it possible to utilize the properties inherent in the oxide arranged between the two gates is that this oxide is namely a poor conductor when the upper gate is negative with respect to the lower gate is biased, but makes a better conductor in the opposite situation.

In the cell according to the invention with the above floating gate, the asymmetry of the dielectric conductivity property is exploited. That is, in the state in which the electric field has the higher modulus or magnitude value, it is in the direction in which the dielectric has the lowest conductivity, while it is in conventional cells behaves in reverse.

The effect is increased if, according to a preferred embodiment of the invention, that between the two Gates arranged dielectric is not only oxide but oxide with silicon nitride arranged over it. Testing showed that such a coupling increases the difference in behavior in both directions of conduction.

From all this the final result is that it is possible for a given functional

Efficiency of producing a cell with a thinner dielectric and consequently with reduced overall dimensions.

The invention and developments of the invention will now be explained in more detail with reference to embodiments. In the Drawings show:

Fig. 1 shows the structural design of an inventive fused cell;

Fig. 2 is a diagram showing the operation of the cell of Fig. 1; and

3 shows an oxide-nitride coupling that acts as a dielectric between the two gates of the cell according to Fig '. 1 can be used.

Fig. 1 shows a fused cell with a monocrystalline silicon substrate 1, which is doped with a Drain zone 2, a doped source zone 3 and a channel zone 4 located therebetween is provided.

A floating polycrystalline silicon gate 5 is arranged above the substrate 1, with a part 6 which has a region 7 near the drain zone 2, and a further part 8 which is arranged above the control and selection gate 9 and the source zone 3 is adjacent.

Silicon oxide 10 surrounds the two gates 5 and 9 and forms a thin oxide zone 11 under region 7 of the floating gates and a dielectric layer 12 between the two superimposed gates.

The properties of the oxide cause the cell to behave differently depending on the Floating gate bias state. When the floating gate has a more positive potential than that Having control gate, the oxide becomes a conductor at a relatively lower nominal electric field. this however, it is the state in which it is difficult to generate a high electric field. If on the other hand that If the floating gate has a more negative potential than the control gate, the oxide will only be at higher electrical Fields a ladder. It is thus possible to design cells with a thinner dielectric, since they have a Withstand higher electric field than it would if the floating gate were charged with electrons without causing a loss of charge.

The two situations are represented by curves A and B in Fig. 2, with the voltage V on the abscissa and the current I is plotted on the ordinate.

The behavior described above is further increased if the dielectric 12 is made not only of oxide but of an oxide-nitride double layer is made, as shown in Fig. 3, where the oxide with 12 'and the nitride marked with 12 ".

The manufacturing process for the cell makes it possible to have a thick oxide between the monocrystalline silicon and to grow the first layer of polycrystalline silicon and a thinner dielectric, i.e. Oxide, or oxide and nitride, between the monocrystalline silicon and the second layer of polycrystalline Silicon.

The usefulness of distinguishing these two dielectrics

licher thickness available so that one will be able to is, the high-voltage circuitry with thicker oxide and thus with higher breakdown voltages and the Low-voltage circuitry with thinner oxide or with the oxide-nitride double layer to produce Creating faster circuits will be readily apparent to those skilled in the art.

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Claims (3)

Priority; , October 23, 1984, Italy, No. 23282 A / 82 K 30 137 SM6 Merged non-volatile memory cell claims 1. Fused non-volatile memory cell with a doped drain and source zones (2, 3) having silicon substrate (1), a floating gate (5), a one-piece control and selection gate (9) and one between the gates (5, 9) arranged dielectric (12; 12 ', 12 "),
characterized, that the floating gate (5) is arranged above the control and selection gate (9). 2. Memory cell according to claim 1, characterized in that the dielectric (12) is formed from silicon oxide. 3. Memory cell according to claim 1, characterized in that the dielectric is formed from silicon oxide (12 ') and silicon nitride (12 ") arranged above it.