GB2152284A - Semiconductor device and protective circuit - Google Patents

Semiconductor device and protective circuit Download PDF

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Publication number
GB2152284A
GB2152284A GB08432417A GB8432417A GB2152284A GB 2152284 A GB2152284 A GB 2152284A GB 08432417 A GB08432417 A GB 08432417A GB 8432417 A GB8432417 A GB 8432417A GB 2152284 A GB2152284 A GB 2152284A
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Prior art keywords
circuit
protective circuit
drain structure
semiconductor device
diffusion
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GB08432417A
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GB8432417D0 (en
GB2152284B (en
Inventor
Hideotoshi Iwai
Kazumichi Mitsusada
Masamichi Ishihara
Tetsuro Matsumoto
Kazuyuki Miyazawa
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Hitachi Ltd
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Hitachi Ltd
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Publication of GB2152284A publication Critical patent/GB2152284A/en
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Publication of GB2152284B publication Critical patent/GB2152284B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical

Abstract

A semiconductor device has an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate (20). The internal circuit includes MIS elements and has a double-diffused drain structure (29,30), while the protective circuit has a single-diffused drain structure (31,32). The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors (31) and clamping MIS elements (32). The single-diffused drain structure of the protective circuit and the double-diffused drain structure of the internal circuit may be achieved by either scanning the ion implanting apparatus to avoid ion implantation into the region of the protective circuit, or forming a photoresist film over the region of the protective circuit to prevention implantation into the protective circuit region, during the formation of the first layer 29 of the double-diffused drain structure. <IMAGE>

Description

SPECIFICATION Semiconductor device and method of fabrication thereof The present invention relates to a semiconductor device having two circuits on the same semiconductor substrate and to a method offabrication of such a circuit.
Miniaturisation of semiconductor devices (ICs) has been attempted to increase their operating speed and improve their integration density. MOS elements (MOSFETs), which are typical examples of MIS elements (MISFETs), are no exception. To miniaturise MOS elements, the thickness of their gate oxide films has been reduced and the length oftheir channels has become shorterand shorter. This meansthata relatively strong electric field is generated within the device, so that injection of hot carriers into the gate oxide film occurs, and the threshold voltage shifts or there is a degradation of mutual conductance.
A double-diffused drain structure such as that shown in Figure 1 ofthe accompanying drawings has been proposed to solve these problems. Figure 1 is a section through a typical N-channel MOSFET. A P-type silicon semiconductor substrate 1 has a silicon dioxide (SiO2) film 2, a gate oxide film 3 and a gate electrode 4 formed thereon. In orderto reduce the strong electric field in the proximity ofthe drain, both drain and source have a double-diffused drain structure consisting of an N--type layer 5 of phosphorous (P) and an N±type layer 6 of arsenic (As) (referfor example to the aricle by E. Takeda, et al, entitled "An As-P (N±N) Double Diffused Drain MOSFETforVLSl's", published in the Digest of Technical Papers, Symp. on VLSI Technology, OISO, Japan, pp. 40-41 (Sept. 1982)).
A protective circuit is usuallyformed on the same semiconductor substrate to protect the MIS element from abnormal signals from outside the IC. As shown in Figure 12 of the accompanying drawings, the protective circuit (e.g., electrostatic protective circuit) is a circuit to preventthe destruction of the gate insulating film of a MISFET71 of a first stage inverter 68, the gate electrode of which is connected to a bonding pad 8 through a resistor 10. Destruction occurs when electrostatic energy is applied to the bonding pad.
Acircuitsuch as that represented by the equivalent circuit diagram of Figure 2 ofthe accompanying drawings is a typical protective circuit 9 used for protecting circuits other than the protective circuit, e.g. an internal circuit of an IC. Asignal tothe internal circuit is applied to a bonding pad 8 through a diffusion resistor 10, one end of which is connected to the pad 8, and a clamping MOSFET 11 whose gate and source are earthed is connected to the junction between the resistor 10 and the internal circuit.
The inventors ofthe present invention have produced sample semiconductor devices of a doublediffused drain structure, and have discovered the following problem.
In this semiconductor device, the protective circuit 9 has also a double-diffused drain structure. Asection through the circuit 9 is shown in Figure 3 of the accompanying drawings. A P-type silicon semicon ductorsubstrate 12, has an isolation SiO2film 13, a resistor 10, a clamping MOSFET 11, a source region 14,a gate oxide film 15, a gate electrode 16, a phosphosilicate glass (PSG)film 17 and 18 an aluminium electrode formed thereon. Both the diffused resistor 10 and the semiconductor regions ofthe source and drain regions of the clamping MOSFET 11 have a double-diffused drain structure, and consist of an N±typelayerandan N--type layer.
In the semiconductor device of this kind, however, destruction of the insulating film of a MlSFETforming a first stage inverter and having a double-diffused drain tends to occur. This is because the backward breakdown voltage at the junction of a MlSFET(Diode) and having a double-diffused drain rises, the electrostatic energy is applied to the insulating film before it can leak to a substrate by breakdown of the clamping MISFET.
The present invention seeks to overcome, or at least ameliorate these problems, by forming a first circuit, e.g. an internal circuit such as a memory cell, with a double-diffused drain structure, and a second circuit, e.g. the protective circuit, with a single-diffused drain structure. The second circuit may be an electrostatic protective circuit which, as mentioned above, protects thefirstcircuitfrom damage dueto abnormal external signals. Such a device reduces degradation of characteristics due to hot carriers, and also reduces degradation of the destruction voltage. In this way the field intensity action upon the gate oxide film of e.g. a clamping MOSFET may be reduced.
The present invention also proposes a method of fabricating such a semiconductor device by forming a first diffusion layerforthe first circuit and subsequent Iyformingaseconddiffusion layerforthefirstcircuit and a diffusion layerforthe second circuit. In this way the first circuit is provided with a double-diffused drain structure whilstthe second circuit has a singlediffused structure.
The two diffusion layers ofthefirstcircuit may be formed either byfirst masking the second circuit for the formation ofthefirstdiffusion layer, and then removing the mask, or by selective ion implantation scanning.
Embodiments ofthe invention will now be described in detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a section through an N-channel MIS elementwith a double-diffused drain structure and has already been described; Figure 2 is an electric equivalent circuit diagram of an example of an electrostatic protective circuit and has already been described; Figure 3 is a section through a device corresoponding to the equivalent circuit of Figure 2 and has already been described; Figure 4 is a plan view of an example ofthe chip pattern of a DRAM provided with an electrostatic protective circuit and an internal circuit on the same semiconductor substrate; Figues Sto 8 are sections through a semiconductor device, showing the fabrication method in accordance with one embodiment of the present invention;; Figures 9 and 10 are schematic plan views corresponding to the electrostatic protective circuit and the internal circuit of Figure 8, respectively; Figure 11 is a graph of experimental results showing the dielectric breakdown voltage of an electrostatic protective circuit with a single-diffused drain structure, compared with that of an electrostatic protective circuit with a double-diffused drain structure; Figure 12 is a circuit diagram showing an electrostatic protective circuit and a specific internal circuit protected thereby; Figures 13 and 14are respectively circuit diagrams showing the present invention applied to a MISFET composing a first stage of an input buffer and a MlSFETcomposing a final stage of an output buffer.
Figures 15,16, and l7showcircuitdiagrams of CMISICS embodying the present invention; and Figure 18 is a cross sectional view of part of the circuit ofthe circuit of Figure 15 according to a first arrangement; and Figure 19 is a cross sectional view of part ofthe circuit of Figure 15 according to a second arrangement.
Afirst embodiment of a semiconductor device and a method of fabricating it in accordance with the present invention will now be described with referenceto Figures4to 10. However, such description exemplifies, not limits the invention.
Figure 4 shows an example of the layout of a chip 7 of a dynamic random access memory (DRAM) in accordance with one embodiment of the invention.
The DRAM consists of bonding pads 8, a protective circuit 9 provided for each bonding pad 8, a signal generation circuit 100 which generates read and write timing signals, etc., a memory array 101 in which MIS elements are used as memory cells, and column and row decoders 102.
Figures 5 to 8 are cross-sectional views showing, step-by-step, the process of fabricating a semiconductor device being an embodiment of the present invention. The protective circuit is shown on the left of each drawing and a memory cell, which is partofthe internal circuit, is shown on the right. Figure 8 is a section through a completed semiconductor device, and Figures 9 and 10 are schematic plan views ofthe semiconductor device of Figure 8.
Figure 5 shows the state in which the process has been completed up to the formation of the gate electrode ofthe MOSFET of the DRAM. This state may be completed by conventional techniques shown in Figure 5 are a semi-conductorsubstrate 20, a gate oxide film 21, and a gate electrode 22. The semicon ductorsubstrate 20 is, e.g., a P-type monocrystalline silicon substrate having a (100) crystal plane, for example, and the gate oxide film 21 is an SiO2film, for example. The gate electrode 22 is a conductive layer forming a second layer, and is formed by depositing polycrystalline silicon by chemical vapour deposition (CVD), and then diffusing e.g. phosphorus ions to form polycrystalline silicon of a reduced resistance.The gate electrode may consist of a iayer of a metal which has a high melting point, a layer of the silicide of such a metal, or a two-layered structure consisting of polyc rystalline silicon and the silidide of a metal with a high melting point. The circuit shown in Figure 2 illustrates an example ofthe protective circuit on the left of Figure 5, and the memory cell of the DRAM is shown as one example of an internal circuit on the right of Figure 5.
Athick oxide film 23 providing isolation is formed by selective thermal oxidation of the surface ofthe silicon substrate 20, for example. A silicon nitride (Si3N4) film 25 acting as a dielectric film of a storage capacitor is formed on the surface ofthefield oxide film 23 on the memory cell side, and also on the surface of a thin SiO2 film 24that continues from the film 23 A polycrystal- line silicon electrode 27 is formed on thethin film 25 through an SiO2fiIm 26 and is diffused with e.g phosphorus ions so as to reduce its resistance. The conductive layer which is the first layer consisting of this polycrystalline silicon electrode 27 forms one of the electrodes ofthe capacitor ofthe memory cell.Ion implantation for an inversion prevention layer (that is, a channel stopper layer), orforcontrolling the threshold voltage, etc., has already been completed by this stage.
Next, as shown in Figure 6, a photoresistfilm 28 is selectivelyformed overthe surface of the protective circuit alone, by a photolithographic process. More specifically, the photoresistfilm 28 (1 clam) is formed onlyoverthe region Ain Figure 4. Ion implantation is then effected using this photoresistfilm 28 as a mask, in orderto form N--type diffusion layers 29 which act as source and drain regions in the memory cell. This ion implantation uses phosphorus ions as the N-type impurity, for example. The impurity does is 1 x 1014/cm2 and the implantation energy is 50 KeV.
Arsenic ions can be used as the impurity.
Referring to Figure7,thephotoresistfilm 28 is removed, and then N-type impurity ions such as arsenic ions are implanted to form an N±type layer 30, and hence a double-diffused drain structure. This ion implantation also forms a diffusion resistance layer 31 of the protective circuit, as well as a source-drain region 32 of the clamping MOSFET. The impurity does is 8 x 1015/cm2 and the implantation energy is 80 KeV. Phosphorus ions can be used as the impurity.
As can be appreciated, the diffusion resistor can be formed from a polysilicon layer, e.g., formed overthe semiconductorsubstrate.
As can be seen from Figures 6 and 7, the protective circuit has a single-diffused drain structure while the internal circuit (memory cell) has a double-diffused drain structure. In this case, the photoresistfilm 28 is selectivelyformedto prevent the implantation of the N--type phosphorus ions into the protective circuit.
However,theimplantation of phosphorusionsinto the protective circuit can also be prevented by controlling the scanning of the ion implantation (by avoiding scanning ofthe region includtngthe protective circuit, i.e., region A in Figure 4}. This is relatively easy because the electrostatic protective circuit is usuallyformed in a certain region around the periphery of the chip, as shown in Figure 4, and so inhibitthe ion implantation may be limited by avoiding scanning this region.
After the electrostatic protective circuit of the single-diffused drain structure and the internal circuit ofthedouble-diffused drain structure have thus been formed, a phosphosilicate glass film (PSG film) 33 and an aluminium layer acting as a third conductive layer are formed as shown in Figure 8. The aluminium layer acts as an output electrode 34forthe diffustion resistor 31, an output electrode 35 forthe internal circuit, a source electrode 36, and a data line 37 ofthe memory cell. Afterthe PSG film 33 is formed, photoetching is used to form contact holes for these electrodes, and aluminium sputtering is done to form the electrodes. Finally, a PSG film 38 is formed as a protective film.
Figures 9 and 10 are schematic plan views of the electrostatic protective circuit and internal circuit of Figure 8, respectively.A section along the line B-B of Figure 9 and a section along the line C-C of Figure 10 correspond to the protective circuit region and the internal circuit region of Figure 8, respectively.
In Figure 9 is shown a bonding pad 40, a diffusion layer 41 for an input portion, a contact hole 42, and a diffused resistor43. Also shown is a clamping MOSFET 44 which consists of a region 45 connected electrically to the diffused resistor 43, a gate electrode 46 and a source 47. The region 45 is connected to an aluminium signal line45Bthroughcontacts45A,and the aluminium signal line 45B is electrically connected to the internal circuit. Similarly, the source 47 is connected to an aluminium line 47B through contacts 47A, and one end ofthe aluminium line 4713 is connected to the gate electrode through a contact 48, with the other end earthed.
In Figure 10, a boundary line S0ofthefield oxide film defines the active region of the memory cell, and a polycrystalline silicon word line 51 corresponds to the gate electrode of the MOSFET. Polycrystalline silicon 52 acts as one ofthe electrodes ofthe capacitor ofthe memory cell, and an aluminium electrode 53 is wi red to a contact hole 54 of the data line.
Figure 11 is a graph oftypical experimental data comparing the electrostatic destruction voltage of a protective ci rcuit with a single-diffused drain structure and that of a protective circuitwith the doublediffused drain structure. The percentage accumulative defect ratio is shown along the ordinate, and the electrostatic destruction voltage (V) along the abscissa. The segmented line a denotes the data from devices having a double-diffused drain structure, and the segmented line b data from the devices having a single-diffused drain structure. The voltage resistance ofthe same pin of five samples was examined. It can be seen from the graph that a protective circuit with a single-diffused drain structure exhibits a much better electrostatic destruction voltage.
As described above, since the protective circuit has a single-diffused drain structure and the internal circuit has a double-diffused drain structure, the electric field concentration in the internal circuit and the electric field concentration in the gate oxide film of thefirst stage MISFET ofthe internal circuit can be reduced, ameliorating the problems of hot carriers and of destruction voltage.
Since a mask is appled to the protective circuitto preventthe formation of one of the diffusion layers of the double-diffused drain, the semiconductor device of this invention can be easily fabricated by adding only one photolithographic step.
If alternatively a method is used of locally controlling the ion implantation scanning to avoid the protective circuit, the present invention can be executed by a simple production process.
Although the invention has been described specificallywith reference to an em bodiment thereof, the present invention is not limited thereto, but can be modified in various ways. For example, the protective circuit in the embodiment described above consists of one diffused resistor and one clamping MOSFET, but this is not necessary, and the invention can be applied to various protective circuits that utilize the junction breakdown in a diffusion layer and the surface breakdown atthe drain end of a clamping MOSFETto improve the dielectric breakdown voltage.Moreover, the clamping MOSFETcan be replaced by one or two junction diodes. In th is case, the j u nction of the diode is between the P-type substrate and the N±type layer formed simultaneously with the N+4ype layers 30,31 and 32.
Similarly, a DRAM has been described as an example of the internal circuit, butthe internal circuit is not limited to a DRAM, and the invention may be applied to other circuits provided with MIS elements which have at least a double-diffused drain structure.
Thus, the present invention can be embodied in a MISFET having a single-diffused drain structure, applied to a MlSFETforming the first stage of an input buffer and to a MlSFETforming a final stage of an output buffer. Circuit diagrams for such MISFETS having the single-diffused structure, applied to the MlSFETforming the first stage of an input buffer and the MlSFETforming the final stage of an output buffer are shown in Figures 13 and 14. In Figures 13 and 14, respectively, there are shown an input pad 81 and an output pad 82, and the structure within dotted lines 83, 84 represents the single-diffused drain structure.
Moreover, the invention may also be applied to N-channel MISFETs of a CMISIC, where N-channel MOSFETsareformed in a P-well region ora Psubstrate.
Figures 15,16and 17 showthe circuit diagrams for such a CMISIC. The structure within dotted lines 85,86 and 87 has a single-diffused drain structure.The structures of the MISFETS 88,89, and 90 in Figure 15 are shown in more detail in Figure 18. The N-channel MISFET 89 has a double diffused drain structure with an N±type layer 58 and Nfltype layer 59, which are formed in a P--type substrate 56. P±type regions 61 act as source and drain regions of the P-channel MISFET 90 formed in an N --type well region 57. The MISFET88 has a single diffused drain structure with an N±type layer 60 formed in the substrate 56. A diode 91 has a same structure as the MISFET 88.
Junction diodes 93,94 (Figure 16)96 and 97 (Figure 17) are formed between a P-type substrate and N±type layers such as the N+4ype layers 60 shown in Figure 18. The N±type layers 60 are drains of MISFETS and are formed simultaneously. If a resistor 92 is made of an N±type layer, e.g. simultaneously with layers 60, the diode 94 can be formed parasitically between the resistor92 and the P-type substrate 56.
Moreover, the invention can be applied to devices in which the N-channel MISFETS 91 have the structure shown in Figure 19. The source and/or drain region of the MISFET 91 isformed byan N--type layer 64 formed in self-alignmentwith a gate electrode 65 and an N±type layer 63 formed in self-alignmentwith a side wall spacer 62 and the gate electrode 65. The MISFET 91 replaces the MISFET 89, for example.
Thus, while the foregoing description has been directed to a DRAM and its protective circuit, the present invention may be applied to ordinary MOS integrated circuits such as DRAMS (e.g., 256 K bits DRAMS), SRAMs, MOS logic circuits, and so forth.
While we have shown and described embodiments ofthe present invention, it should be understood that the invention is not limited thereto but is susceptible of numerous changes and modifcations as is apparent to one having ordinary skill in the art and we therefore do not wish to be limited to the details shown and described herein.

Claims (19)

1. Asemiconductor device comprising afirst circuit including an MIS element, and a second circuit electrically connected to the first circuit, the first and second circuit being on the same semiconductor substrate, the first circuit having a double-diffused drain structure and the second circuit having a single-diffused drain structure.
2. A semiconductor device according to claim 1, wherein the first circuit is an internal circuit, and the second circuit is an electrostatic protective circuit, the electrostatic protective circuit being to protect the internal circuit from abnormal external signals.
3. A semiconductor device according to claim 2, wherein the electrostatic protective circuit includes at least one diffused resistor and at least one clamping MIS element.
4. A semiconductor device according to claim 3, wherein the diffused resistor has a single-diffused drain structure.
5. Asemiconductordevice according to claim 3 or claim 4 having an input bonding pad, the resistor being electrically connected to the internal circuit and to the bonding pad.
6. A semiconductor device according to any one of claims 2 to 5, wherein the electrostatic protective circuit is electrically connected to an output bonding pad.
7. A semiconductor device according to any one of claims 2to 6, wherein the internal circuit has a dynamic RAM element.
8. A semiconductor device substantially as herein described with reference to and as illustrated in Figure 4,orFigures5to10,oranyoneofFigures15to19.
9. Amethodoffabricating asemiconductordevice having a first circuit including a MIS element and a second circuit electrically connected to the first circuit, the first and second circuits being formed on the same semiconductor substrate; the method including forming a first diffusion layer forthe MIS element and subsequently forming a second diffusion layerforthe MIS element and a diffusion layerforthe second circuit, so that the first circuit has a double-diffused drain structure and the second circuit has a single-diffused drain structure.
10. A method according to claim 9, wherein a mask is formed over the second circuit priorto the formation ofthefirstdiffusion layer, andthusthe mask is removed after the formation ofthe first diffusion layer but before the formation of the second diffusion layer.
11. A method according to claim 10, wherein said mask is made from a photoresistfilm.
12. A method according to claim 9, wherein the first diffusion layer is formed by ion implantation scanning over only the first circuit, and the second diffusion layer and the diffusion layerforthe second circuit are formed by ion implantation scanning over the entire surface of the device.
13. A method according to any one of claims 9 to 12, wherein the first circuit is an internal circuit, and the second circuit is an electrostatic protective circuit, the electrostatic protective circuit being to protect the internal circuitfrom abnormal external signals.
14. A method according to any one of claims 9 to 13, wherein the first and second diffusion layers, and the diffusion layer of the second circuit, are each formed by ion implantation.
15. A method according to claim 14, wherein the first diffusion layer is an N -layerformed by ion implantation of phosphorus ions, and the second diffusion layerandthe diffusion Iayerofthe second circuit are N+ layers formed by ion implantation of arsenic ions.
16. A method according to any one of claims 9to 15, wherein the second diffusion layer and the diffusion layer ofthe second circuit are formed simultaneously.
17. A method according to any one of claims 9to 16, wherein the electrostatic protective circuit is positioned at a peripheral portion of the semiconductorsubstrate in an offset arrangement.
18. A method of fabricating a semiconductor device substantially as any one herein described with reference to Figures 4to 14 of the accompanying drawings.
19. Adeviceformedbythe method of any one of claims 9 to 18.
GB08432417A 1983-12-26 1984-12-21 Semiconductor device and protective circuit Expired GB2152284B (en)

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JP58243801A JPH0646662B2 (en) 1983-12-26 1983-12-26 Semiconductor device

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GB2152284A true GB2152284A (en) 1985-07-31
GB2152284B GB2152284B (en) 1988-01-06

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KR (1) KR930001564B1 (en)
DE (1) DE3446928A1 (en)
FR (1) FR2561042B1 (en)
GB (2) GB2152284B (en)
HK (2) HK41790A (en)
IT (1) IT1179545B (en)

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EP0266768A1 (en) * 1986-11-07 1988-05-11 Kabushiki Kaisha Toshiba Manufacturing method for forming a MOS transistor by self-alignment of the source/drain regions
US5142345A (en) * 1989-04-13 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor
GB2274203A (en) * 1993-01-07 1994-07-13 Seiko Epson Corp Semiconductor device protection

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JPS62169468A (en) * 1986-01-22 1987-07-25 Nec Corp Semiconductor integrated circuit device
JP2953192B2 (en) * 1991-05-29 1999-09-27 日本電気株式会社 Semiconductor integrated circuit

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Cited By (6)

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EP0266768A1 (en) * 1986-11-07 1988-05-11 Kabushiki Kaisha Toshiba Manufacturing method for forming a MOS transistor by self-alignment of the source/drain regions
US5142345A (en) * 1989-04-13 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor
GB2274203A (en) * 1993-01-07 1994-07-13 Seiko Epson Corp Semiconductor device protection
GB2274203B (en) * 1993-01-07 1996-08-07 Seiko Epson Corp Semiconductor device
US5614752A (en) * 1993-01-07 1997-03-25 Seiko Epson Corporation Semiconductor device containing external surge protection component

Also Published As

Publication number Publication date
GB8702881D0 (en) 1987-03-18
HK48090A (en) 1990-06-29
GB8432417D0 (en) 1985-02-06
FR2561042A1 (en) 1985-09-13
GB2186426B (en) 1988-01-06
GB2186426A (en) 1987-08-12
IT8424246A0 (en) 1984-12-24
KR850005166A (en) 1985-08-21
JPH0646662B2 (en) 1994-06-15
KR930001564B1 (en) 1993-03-04
JPS60136374A (en) 1985-07-19
IT1179545B (en) 1987-09-16
HK41790A (en) 1990-06-08
DE3446928A1 (en) 1985-07-04
GB2152284B (en) 1988-01-06
FR2561042B1 (en) 1988-11-10

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